A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 184

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
6 - 2
Revision
Revision 5
(December 2010)
Table 2-2 • Analog Maximum Ratings
voltage (relative to ground) was changed from –11 to –0.3 (SAR 28219).
Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays
to change the values for 100ºC.
Power-down and Sleep modes, and all associated notes, were removed from
Table 2-8 • Quiescent Supply Current Characteristics
were renamed to IDC1 and IDC2 (SAR 29478). These modes are no longer supported.
A note was added to the table stating that current monitors and temperature monitors
should not be used when Power-down and/or Sleep mode are required by the
application.
The
29479).
Values for PAC9 and PAC10 for LVDS and LVPECL were revised in
Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings*.
Values for PAC1 through PAC4, PDC1, and PDC2 were added for A2F500 in
Table 2-13 • Different Components Contributing to Dynamic Power Consumption in
SmartFusion Devices
Power Consumption in SmartFusion Devices
The equation for
revised to add P
section
Information in
Settings
Characteristics—Software Default Settings
updated.
Available values for the Std. speed were added to the timing tables from
3.3 V LVTTL / 3.3 V LVCMOS High Slew
One or more values changed for the –1 speed in tables covering 3.3 V LVCMOS, 2.5 V
LVCMOS, 1.8 V LVCMOS, 1.5 V LVCMOS, Combinatorial Cell Propagation Delays,
and A2F200 Global Resources.
Table 2-79 • A2F500 Global Resource
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: T
VCC = 1.425 V
The programmable analog specifications tables were revised with updated
information.
Table 4-1 • Supported JTAG Programming Hardware
indicate "planned support" for several of the items in the table.
The note on JTAGSEL in the
that SoftConsole selects the appropriate TAP controller using the CTXSELECT JTAG
command. When using SoftConsole, the state of JTAGSEL is a "don't care" (SAR
29261).
The
A2F060 function with the A2F200 function (SAR 29353).
The "Handling When Unused" column was removed from the
table for A2F200 and A2F500 (SAR 29691).
"288-Pin CSP"
"Power-Down and Sleep Mode Implementation" section
is new (SAR 29462).
(applicable to FPGA I/O banks) and
Table 2-23 • Summary of I/O Timing Characteristics—Software Default
was revised (SAR 27585).
MSS
"Total Dynamic Power Consumption—P
and
. The
and
"256-Pin FBGA"
Table 2-14 • Different Components Contributing to the Static
"Microcontroller Subsystem Dynamic Contribution—P
"In-System Programming" section
Changes
R e vi s i o n 6
is new.
was revised. The recommended CM[n] pad
pin tables for A2F060 are new, comparing the
to
Table 2-90 • JTAG 1532
(applicable to MSS I/O banks) was
Table 2-24 • Summary of I/O Timing
was revised by adding a note to
(SAR 29479). IDC3 and IDC4
DYN
"
in
"256-Pin FBGA"
was revised to state
was deleted (SAR
(SAR 29331).
"SoC Mode"
Table 2-37 •
was revised
Table 2-9 •
J
= 85°C,
MSS
was
and
pin
"
2-31
2-75
2-10,
2-12,
2-14,
Page
2-10
2-11
2-13
2-18
2-25
2-74
2-60
2-73
2-84
5-17
5-49
N/A
2-2
2-9
4-5
4-5
to
to