A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 187

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
Revision 2
(May 2010)
Revision 1
(March 2010)
Revision 0
(March 2010)
Embedded nonvolatile flash memory (eNVM) was changed from "64 to 512 Kbytes" to
"128 to 512 Kbytes" in the
"SmartFusion Family Product Table"
The main oscillator range of values was changed to "32 KHz to 20 MHz" in the
"Microcontroller Subsystem (MSS)" section
Table"
The value for t
comparators listed in the
The number of PLLs for A2F200 was changed from 2 to 1 in the
Product Table"
Values for direct analog input, total analog input, and total I/Os were updated for the
FG256 package, A2F060, in the
column was removed from the table (SAR 26005).
The Speed Grade section of the
(SAR 25257).
The
free packaging and application (junction temperature range).
Table 2-3 • Recommended Operating Conditions
temperature) was replaced with T
PDC5 was deleted from
Power Consumption in SmartFusion
The formulas in the footnotes for
Resistances
The values for input biased current were revised in
Performance
The
bit mode from 600 Ksps to 550 Ksps.
The A2F060 device was added to product information tables.
The
speed grade 1. Pre-production was removed from the application ordering code
category.
The
The
Diagram"
The "VCCI" parameter was renamed to "VCCxxxxIOBx."
"Advanced I/Os" were renamed to "FPGA I/Os."
Generic pin names that represent multiple pins were standardized with a lower case x
as a placeholder. For example, VAREFx designates VAREF0, VAREF1, and VAREF2.
Modes were renamed as follows:
Operating mode was renamed to SoC mode.
32KHz Active mode was renamed to Standby mode.
Battery mode was renamed to Time Keeping mode.
Table entries have been filled with values as data has become available.
"SmartFusion Block Diagram"
"Datasheet Categories" section
"Product Ordering Codes"
"Analog Front-End (AFE)" section
"Product Ordering Codes"
(SAR 24906).
table, which is new.
were revised.
Specification.
(SAR 25093).
PD
was changed from 50 ns to 15 ns for the high-speed voltage
"Analog Front-End (AFE)" section
Table 2-14 • Different Components Contributing to the Static
table was revised to add "blank" as an option for lead-
table was updated to removed Std. speed and add
"Package I/Os: MSS + FPGA I/Os"
J
"Microcontroller Subsystem (MSS)" section
was revised.
(junction temperature).
was updated, referencing the
(SAR 26005).
Devices.
"Product Ordering Codes"
Changes
R e v i s i o n 6
was updated to change the throughput for 10-
Table 2-28 • I/O Weak Pull-Up/Pull-Down
and the
SmartFusion Intelligent Mixed Signal FPGAs
"SmartFusion Family Product
Table 2-91 • Current Monitor
was revised. Ta (ambient
(SAR 26005).
"SmartFusion Family
"SmartFusion Block
table was revised
table. The Max.
and
1-4,
Page
2-13
2-27
2-75
N/A
N/A
I,
I,
2-3
VI
VI
VI
IV
III
II
I
I
II
II
IV
6 -5