A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 55

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-13 • LVPECL Circuit Diagram and Board-Level Implementation
Table 2-65 • Minimum and Maximum DC Input and Output Levels
Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-67 • LVPECL
DC Parameter
VCCFPGAIOBx Supply Voltage
VOL
VOH
V
V
V
V
V
Input Low (V)
1.64
*
Speed Grade
Std.
–1
Note:
OUTBUF_LVPECL
IL
ODIFF
OCM
ICM
IDIFF
Measuring point = V
, V
IH
For the derating values at specific junction temperature and voltage supply levels, refer to
page 2-9
Worst Commercial-Case Conditions: T
Worst-Case VCCFPGAIOBx = 3.0 V
Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires
that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVDS implementation because the output standard
specifications are different.
Timing Characteristics
for derating values.
Output Low Voltage
Output High Voltage
Input Low, Input High Voltages
Differential Output Voltage
Output Common-Mode Voltage
Input Common-Mode Voltage
Input Differential Voltage
FPGA
trip.
See
t
DOUT
0.60
0.50
Description
Table 2-21 on page 2-24
Input High (V)
N
P
Bourns Part Number: CAT16-PC4F12
1.94
100 Ω
100 Ω
1.76
1.46
t
DP
J
187 W
= 85°C, Worst-Case VCC = 1.425 V,
for a complete table of trip points.
0.625
1.762
Min.
0.96
1.01
300
1.8
R e v i s i o n 6
0
Z
Z
0
0
3.0
Measuring Point* (V)
= 50 Ω
= 50 Ω
Max.
1.27
2.11
0.97
1.98
2.57
0.04
0.03
3.3
t
DIN
Cross point
100 Ω
SmartFusion Intelligent Mixed Signal FPGAs
0.625
1.762
Min.
1.01
1.06
1.92
300
0
3.3
N
P
Max.
1.43
2.28
0.97
1.98
2.57
3.6
1.76
1.46
t
PY
FPGA
+
–
0.625
1.762
Min.
1.30
2.13
1.01
300
0
V
3.6
INBUF_LVPECL
REF
Figure
Max.
2.57
1.57
2.41
0.97
1.98
3.9
(typ.) (V)
Table 2-7 on
–
Units
ns
ns
2-13. The
Units
mV
V
V
V
V
V
V
V
2- 43