A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 66

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Figure 2-22 • Output DDR Timing Diagram
Table 2-76 • Output DDR Propagation Delays
2- 54
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
Data_R
DDROCLKQ
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
CLK
Data_F
CLR
Out
DDOMAX
For specific junction temperature and voltage supply levels, refer to
6
Worst Commercial-Case Conditions: T
Timing Characteristics
t
DDROCLR2Q
1
t
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width High for the Output DDR
Clock Minimum Pulse Width Low for the Output DDR
Maximum Frequency for the Output DDR
DDROREMCLR
t
DDROREMCLR
7
2
t
t
DDROCLKQ
DDROHD1
7
t
DDROSUD2
8
Description
3
J
2
= 85°C, Worst-Case VCC = 1.425 V
R e visio n 6
t
DDROHD2
8
Table 2-7 on page 2-9
4
9
3
t
DDRORECCLR
9
10
4
for derating values.
5
0.71
0.38
0.38
0.00
0.00
0.81
0.00
0.23
0.22
0.36
0.32
350
–1
10
Units
11
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns