A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 9

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1 – SmartFusion Device Family Overview
Introduction
General Description
The SmartFusion family of intelligent mixed signal FPGAs builds on the technology first introduced with
the Fusion mixed signal FPGAs. SmartFusion devices are made possible by integrating FPGA
technology with programmable high-performance analog and hardened ARM
microcontroller blocks on a flash semiconductor process. The SmartFusion family takes its name from
the fact that these three discrete technologies are integrated on a single chip, enabling the lowest cost of
ownership and smallest footprint solution to you.
Microcontroller Subsystem (MSS)
The MSS is composed of a 100 MHz Cortex-M3 processor and integrated peripherals, which are
interconnected via a multi-layer AHB bus matrix (ABM). This matrix allows the Cortex-M3 processor,
FPGA fabric master, Ethernet message authentication controller (MAC), when available, and peripheral
DMA (PDMA) controller to act as masters to the integrated peripherals, FPGA fabric, embedded
nonvolatile memory (eNVM), embedded synchronous RAM (eSRAM), external memory controller
(EMC), and analog compute engine (ACE) blocks.
SmartFusion devices of different densities offer various sets of integrated peripherals. Available
peripherals include SPI, I
MAC, timers, phase-locked loops (PLLs), oscillators, real-time counters (RTC), and peripheral DMA
controller (PDMA).
Programmable Analog
Analog Front-End (AFE)
SmartFusion devices offer an enhanced analog front-end compared to Fusion devices. The successive
approximation register analog-to-digital converters (SAR ADC) are similar to those found on Fusion
devices. SmartFusion also adds first order sigma-delta digital-to-analog converters (SDD DAC).
SmartFusion can handle multiple analog signals simultaneously with its signal conditioning blocks
(SCBs). SCBs are made of a combination of active bipolar prescalers (ABPS), comparators, current
monitors and temperature monitors. ABPS modules allow larger bipolar voltages to be fed to the ADC.
Current monitors take the voltage across an external sense resistor and convert it to a voltage suitable
for the ADC input range. Similarly, the temperature monitor reads the current through an external PN-
junction (diode or transistor) and converts it internally for the ADC. The SCB also includes comparators
to monitor fast signal thresholds without using the ADC. The output of the comparators can be fed to the
analog compute engine or the ADC.
Analog Compute Engine (ACE)
The mixed signal blocks found in SmartFusion are controlled and connected to the rest of the system via
a dedicated processor called the analog compute engine (ACE). The role of the ACE is to offload control
of the analog blocks from the Cortex-M3, thus offering faster throughput or better power consumption
compared to a system where the main processor is in charge of monitoring the analog resources. The
ACE is built to handle sampling, sequencing, and post-processing of the ADCs, DACs, and SCBs.
2
C, and UART serial ports, embedded FlashROM (EFROM), 10/100 Ethernet
R e v i s i o n 6
®
Cortex™-M3
1 -1