A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 49

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-52 • Minimum and Maximum DC Input and Output Levels
Table 2-53 • Minimum and Maximum DC Input and Output Levels
Figure 2-9 • AC Loading
Table 2-54 • AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
2 mA
4 mA
6 mA
8 mA
12 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
1.5 V
LVCMOS
Drive
Strength
2 mA
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Input Low (V)
0
*
Measuring point = V
Min.
–0.3
Min.
–0.3
0.3
0.3
0.3
0.3
V
V
–
–
–
–
Applicable to FPGA I/O Banks
Applicable to MSS I/O Banks
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VIL
VIL
Test Point
Datapath
0.35 *
0.35 *
0.35 *
0.35 *
0.35 *
0.35*
Max.
Max.
trip.
V
V
Input High (V)
See
1.5
Table 2-21 on page 2-24
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
35 pF
0.65 *
0.65 *
0.65 *
0.65 *
0.65 *
0.65 *
Min.
Min.
V
V
VIH
VIH
Measuring Point* (V)
Enable Path
Test Point
1.575
1.575
1.575
1.575
1.575
1.575
Max.
Max.
V
V
R = 1 K
0.75
VCCxxxxIOBx
for a complete table of trip points.
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
0.25* VCC
R e v i s i o n 6
0.25 *
0.25 *
Max.
VOL
0.25*
0.25*
0.25*
Max.
VOL
V
V
R to VCCxxxxIOBx for t
R to GND for t
35 pF for t
5 pF for t
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
VCCxxxxIOBx
SmartFusion Intelligent Mixed Signal FPGAs
V
HZ
0.75 *
REF
0.75 *
0.75 *
0.75 *
0.75 *
0.75 *
VOH
ZH
Min.
VOH
Min.
V
/ t
V
/ t
HZ
LZ
(typ.) (V)
ZHS
–
/ t
ZH
/ t
ZL
/ t
mA mA
I
/ t
mA mA
ZHS
I
LZ
OL
12 12
OL
6
8
2
2
4
ZLS
/ t
I
ZL
I
OH
OH
2
6
8
2
4
/ t
ZLS
Max.
mA
Max.
I
mA
I
OSL
OSL
16
16
33
39
55
55
C
1
1
LOAD
Max.
Max.
mA
I
mA
I
OSH
OSH
13
25
32
66
66
13
35
1
1
(pF)
µA
µA
15 15
I
I
15 15
15 15
15 15
15 15
15 15
IL
IL
2
2
2- 37
µA
µA
I
I
IH
2
IH
2