XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 35

• Manufacturer Part Number: XC3S1400AN-4FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Buffer Read
Table 3-6: Buffer Read Command Summary (High Frequency, up to 50 MHz)
Spartan-3AN FPGA In-System Flash User Guide
UG333 (v2.1) January 15, 2009
MOSI
MISO
Notes:
1. The Buffer 2 Read command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Buffer Read command (High Frequency) is not supported in simulation.
Pin
Buffer 2 Read
Buffer 1 Read
Command
R
Byte 1
0xD4
0xD6
(1)
The FPGA application can independently access the SRAM data buffers separately from
the ISF memory array, as shown in
reads data directly from the selected buffer. When reading data from the buffer, first load
data into the buffer from an ISF memory page using the
There are two versions of the Buffer Read command. The version that operates up to
50 MHz, shown in
page buffer. This command requires eight “don’t care” bits after specifying the 24-bit
address.
High Address Middle Address
Unused
Caution!
contains only one buffer.
Byte 2
0x00
Buffer 1 Read
Buffer 1 Read
MOSI
MISO
Buffer 2 Read
Buffer 2 Read
CSB
CLK
24-bit Starting Byte Address
The Buffer 2 Read command is not supported on the XC3S50AN FPGA because it
Default Addressing: See
Table 2-2, page 19
Power-of-2 Addressing: See
Table A-3, page 89
High
Table
SPI_ACCESS
Byte 3
Byte Address in Buffer
available on
Buffer 2 not
XC3S50AN
(0xD4): 50 MHz maximum, don’t care byte required
(0xD1): 33 MHz maximum
(0xD6): 50 MHz maximum, don’t care byte required
(0xD3): 33 MHz maximum
3-6, is best for reading multiple contiguous bytes from the SRAM
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Figure 3-5: Buffer Read Command
Low Address
Figure
Byte 4
3-5. The Buffer Read command sequentially
Starting byte address
Automatically increments through
buffer, remains within buffer
Byte 5
Don’t
Care
Byte
XX
Page to Buffer Transfer
Flash Memory Array
Data Byte +0
(most-significant bit first)
Byte 6
Page Buffer Data Bytes
XX
UG333_c3_05_022307
...
..
..
.
.
Data Byte +n
Buffer Read
Byte n+6
command.
XX
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