XC3S1400AN-4FGG484C Xilinx Inc, XC3S1400AN-4FGG484C Datasheet - Page 36

• Manufacturer Part Number: XC3S1400AN-4FGG484C
• Description: IC FPGA SPARTAN-3AN 484FPGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3ANr

Specifications of XC3S1400AN-4FGG484C

• Number Of Logic Elements/cells: 25344
• Number Of Labs/clbs: 2816
• Total Ram Bits: 589824
• Number Of I /o: 372
• Number Of Gates: 1400000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-BBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3: Read Commands
Table 3-7: Buffer Read Command Summary (Low Frequency, up to 33 MHz)
36
MOSI
MISO
Notes:
1. The Buffer 2 Read command is not available in the XC3S50AN because it has only one SRAM page buffer.
2. The Buffer Read command (Low Frequency) is not supported in simulation.
Pin
Buffer 2 Read
Buffer 1 Read
Command
Byte 1
0xD1
0xD3
(1)
The slower version that operates up to 33 MHz, shown in
single, randomly-accessed bytes within the SRAM page buffer. This version has lower
initial latency for single-byte transfers.
It is possible for the FPGA application to read from one SRAM page buffer while the other
buffer is actively transferring data to the main memory from a previous programming
operation, as shown in
To issue a Buffer Read command, the FPGA application must perform the following
actions.
•
•
•
Drive CSB Low while CLK is High or on the rising edge of CLK.
On the falling edge of CLK, serially clock in the appropriate Buffer Read command
code, shown in either
Similarly, serially clock in a 24-bit starting byte address. The page address bits are
ignored.
♦
High Address
Figure 3-6: SRAM Page Buffers Support Read-while-Write Operations
Unused
The starting byte location can be anywhere in the ISF memory array, located on
any page, as shown in
MOSI
MISO
Byte 2
0x00
CSB
CLK
24-bit Starting Byte Address
High
SPI_ACCESS
Default Addressing: See
page 19
Power-of-2 Addressing: See
Table A-3, page 89
Middle Address
Buffer 2 not
available on
XC3S50AN
Figure
www.xilinx.com
Table 3-6
Byte 3
Byte Address in Buffer
3-6.
Figure
or
3-5.
Table
Low Address
Spartan-3AN FPGA In-System Flash User Guide
Byte 4
3-7, most-significant bit first.
Table 2-2,
While transferring data from one
buffer to the Flash Memory Array ...
… the FPGA application can read
data from other buffer.
Flash Memory Array
Data Byte +0
Table
Byte 5
(most-significant bit first)
UG333 (v2.1) January 15, 2009
Page Buffer Data Bytes
XX
3-7, is best for reading
UG333_c3_06_082307
...
...
...
Data Byte +n
Byte 6
XX
R