MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 65

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.20
7.21
Freescale Semiconductor
1
2
3
Hold time (repeated) START condition. After this period, the first
Pulse width of spikes that must be suppressed by the input filter
The master mode I
acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines.
The maximum t
A Fast mode I
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
t
rmax
Bus free time between STOP and START condition
+ t
MSCAN_RX
CAN receive
SU; DAT
Set-up time for a repeated START condition
Freescale’s Scalable Controller Area Network (MSCAN)
Inter-Integrated Circuit Interface (I
data pin
(Input)
Data hold time for I
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
2
Set-up time for STOP condition
= 1000 + 250 = 1250 ns (according to the Standard mode I
C bus device can be used in a Standard mode I
HIGH period of the SCL clock
HD; DAT
LOW period of the SCL clock
clock pulse is generated.
2
SCL Clock Frequency
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
Data set-up time
Characteristic
must be met only if the device does not stretch the LOW period (t
Bus Wake-up detection
Characteristic
Baud Rate
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
2
C bus devices
Figure 26. Bus Wake-up Detection
Table 36. MSCAN Timing
Table 37. I
T
WAKEUP
2
C Timing
T
2
Symbol
BR
C bus system, but the requirement t
WAKEUP
CAN
Symbol
t
t
t
t
t
SU; STO
HD; STA
HD; DAT
SU; DAT
SU; STA
t
t
f
t
HIGH
LOW
BUF
t
SCL
2
SP
t
t
r
f
C) Timing
2
C bus specification) before the SCL line is released.
T
Min
IPBUS
—
Minimum
250
N/A
4.0
4.7
4.0
4.7
4.0
4.7
0
—
—
0
Standard Mode
1
3
LOW
Max
—
1
) of the SCL signal.
Maximum
3.45
1000
100
300
N/A
SU; DAT
—
—
—
—
—
—
—
Mbps
2
Unit
s
> = 250 ns must
Specifications
Unit
kHz
ns
ns
ns
ns
s
s
s
s
s
s
s
65