MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet
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MC56F825x/4x Reference Manual Supports the MC56F8257, MC56F8256, MC56F8255, MC56F8247, MC56F8246, and MC56F8245 Document Number: MC56F825XRM Preliminary Rev. 2, 10/2010 ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 2 Preliminary Freescale Semiconductor ...
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... ADC Channel List Register 3 (ADCCLIST3).................................................................................................58 2.3.7 ADC Channel List Register 4 (ADCCLIST4).................................................................................................60 2.3.8 ADC Sample Disable Register (ADCSDIS)....................................................................................................62 2.3.9 ADC Status Register (ADCSTAT)..................................................................................................................62 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Analog-to-Digital Converter (ADC) Preliminary Page ...
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... ADC Data Processing......................................................................................................................................88 2.4.4 Sequential Versus Parallel Sampling...............................................................................................................89 2.4.5 Scan Sequencing..............................................................................................................................................90 2.4.6 Power Management..........................................................................................................................................91 2.4.6.1 Low Power Modes.........................................................................................................................91 2.4.6.2 Startup in Different Power Modes.................................................................................................92 2.4.6.3 Stop Mode of Operation.................................................................................................................93 2.5 Reset................................................................................................................................................................................94 2.6 Clocks.............................................................................................................................................................................94 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 4 Title Preliminary Page Freescale Semiconductor ...
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... Power Modes....................................................................................................................................................117 3.6.2.1 Wait Mode Operation.....................................................................................................................118 3.6.2.2 Stop Mode Operation.....................................................................................................................118 3.6.2.3 Debug Mode Operation..................................................................................................................118 3.6.3 Hysteresis.........................................................................................................................................................118 3.6.4 Startup and Operation......................................................................................................................................119 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 3 High Speed Comparator (HSCMP) Preliminary Page 5 ...
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... Memory Map and Registers............................................................................................................................................128 5.2.1 Control Register (DACCTRL).........................................................................................................................129 5.2.2 Buffered Data Register (DACDATA [FORMAT=0]).....................................................................................131 5.2.3 Buffered Data Register (DACDATA [FORMAT=1]).....................................................................................131 5.2.4 Step Size Register (DACSTEP [FORMAT=0])..............................................................................................132 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 6 Title Chapter 4 Chapter 5 Preliminary Page Freescale Semiconductor ...
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... Overview.........................................................................................................................................................................143 6.2 Features...........................................................................................................................................................................143 6.3 Modes of Operation........................................................................................................................................................144 6.4 Block Diagram................................................................................................................................................................144 6.5 Memory Map and Registers............................................................................................................................................145 6.5.1 Timer Channel Compare Register 1 (TMRx_COMP1)...................................................................................152 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 6 Quad Timer (TMR) Preliminary Page 7 ...
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... Timer Channel Comparator Status and Control Register (TMRx_CSCTRL).................................................161 6.5.12 Timer Channel Input Filter Register (TMRx_FILT)........................................................................................163 6.5.13 Timer Channel Enable Register (TMRx_ENBL).............................................................................................165 6.6 Functional Description....................................................................................................................................................165 6.6.1 General.............................................................................................................................................................165 6.6.2 Functional Modes.............................................................................................................................................167 6.6.2.1 Stop Mode......................................................................................................................................167 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 8 Title Preliminary Page Freescale Semiconductor ...
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... Timer Compare 1 Interrupts (Available with Compare Load Feature)......................186 6.9.2.1.2 Timer Compare 2 Interrupts (Available with Compare Load Feature)......................186 6.9.2.2 Timer Overflow Interrupts.............................................................................................................186 6.9.2.3 Timer Input Edge Interrupts...........................................................................................................187 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Preliminary Page 9 ...
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... PWM SMx Fractional Value Register 1 (PWMSMnFRACVAL1).................................................................209 7.3.7 PWM SMx Value Register 1 (PWMSMnVAL1)............................................................................................210 7.3.8 PWM SMx Fractional Value Register 2 (PWMSMnFRACVAL2).................................................................211 7.3.9 PWM SMx Value Register 2 (PWMSMnVAL2)............................................................................................211 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 10 Title Chapter 7 Preliminary Page Freescale Semiconductor ...
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... PWM SM3 Status Register (PWMSM3STS)..................................................................................................234 7.3.36 PWM SM3 Interrupt Enable Register (PWMSM3INTEN).............................................................................236 7.3.37 PWM SM3 Output Trigger Control Register (PWMSM3TCTRL).................................................................237 7.3.38 PWM SM3 Fault Disable Mapping Register (PWMSM3DISMAP)...............................................................238 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Preliminary Page 11 ...
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... Fault Filter Register (PWMFFILT)..................................................................................................................258 7.4 Functional Description....................................................................................................................................................259 7.4.1 PWM Capabilities............................................................................................................................................259 7.4.1.1 Center Aligned PWMs...................................................................................................................259 7.4.1.2 Edge Aligned PWMs.....................................................................................................................260 7.4.1.3 Phase Shifted PWMs......................................................................................................................261 7.4.1.4 Double Switching PWMs...............................................................................................................263 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 12 Title Preliminary Page Freescale Semiconductor ...
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... Fault Testing...............................................................................................................290 7.4.3 PWM Generator Loading.................................................................................................................................290 7.4.3.1 Load Enable...................................................................................................................................290 7.4.3.2 Load Frequency..............................................................................................................................290 7.4.3.3 Reload Flag....................................................................................................................................291 7.4.3.4 Reload Errors.................................................................................................................................292 7.4.3.5 Initialization...................................................................................................................................292 7.5 Resets..............................................................................................................................................................................293 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Preliminary Page 13 ...
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... GPIO Interrupt Pending Register (GPIOxA_IPR)...........................................................................................312 9.2.9 GPIO Interrupt Edge Sensitive Register (GPIOxA_IESR)..............................................................................313 9.2.10 GPIO Push-Pull Mode Register (GPIOxA_PPMODE)...................................................................................313 9.2.11 GPIO Raw Data Register (GPIOxA_RAWDATA).........................................................................................314 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 14 Title Chapter 8 Crossbar Switch (XBAR) Chapter 9 Preliminary Page Freescale Semiconductor ...
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... I2C SCL Low Timeout register High (I2Cx_SLT1)........................................................................................333 10.3.11 I2C SCL Low Timeout register Low (I2Cx_SLT2).........................................................................................333 10.4 Functional Description....................................................................................................................................................333 10.4.1 I2C Protocol.....................................................................................................................................................334 10.4.1.1 START Signal................................................................................................................................334 10.4.1.2 Slave Address Transmission..........................................................................................................335 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 10 Inter-Integrated Circuit (I2C) Preliminary Page 15 ...
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... Exit from Low-Power/Stop Modes................................................................................................344 10.4.6.4 Arbitration Lost Interrupt...............................................................................................................345 10.4.6.5 Timeout Interrupt in SMBus..........................................................................................................345 10.4.6.6 Programmable Input Glitch Filter..................................................................................................345 10.4.6.7 Address Matching Wakeup............................................................................................................346 10.5 Initialization/Application Information............................................................................................................................346 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 16 Title Preliminary Page Freescale Semiconductor ...
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... Preambles.......................................................................................................................................368 11.4.4 Receiver...........................................................................................................................................................369 11.4.4.1 Character Length............................................................................................................................369 11.4.4.2 Character Reception.......................................................................................................................369 11.4.4.3 Data Sampling................................................................................................................................370 11.4.4.4 Framing Errors...............................................................................................................................375 11.4.4.5 Baud-Rate Tolerance......................................................................................................................375 11.4.4.6 Slow Data Tolerance......................................................................................................................375 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 11 Preliminary Page 17 ...
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... Block Diagram.................................................................................................................................................386 12.2 Signal Descriptions.........................................................................................................................................................387 12.2.1 External I/O Signals.........................................................................................................................................387 12.2.1.1 MISO (Master In/Slave Out)..........................................................................................................387 12.2.1.2 MOSI (Master Out/Slave In)..........................................................................................................387 12.2.1.3 SCLK (Serial Clock)......................................................................................................................388 12.2.1.4 SS (Slave Select)............................................................................................................................388 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 18 Title Chapter 12 Preliminary Page Freescale Semiconductor ...
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... Error Conditions...............................................................................................................................................410 12.4.4.1 Overflow Error...............................................................................................................................410 12.4.4.2 Mode Fault Error............................................................................................................................412 12.4.4.2.1 Master Mode Fault......................................................................................................413 12.4.4.2.2 Slave Mode Fault........................................................................................................413 12.4.5 Resetting the SPI..............................................................................................................................................414 12.5 Interrupts.........................................................................................................................................................................415 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Preliminary Page 19 ...
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... MSCAN Receive Error Counter Register (CANRXERR)..............................................................................443 13.3.16 MSCAN Transmit Error Counter Register (CANTXERR).............................................................................444 13.3.17 MSCAN Identifier Acceptance Registers (First Bank) (CANIDARn)............................................................445 13.3.18 MSCAN Identifier Mask Registers (First Bank) (CANIDMRn).....................................................................446 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 20 Title Chapter 13 Preliminary Page Freescale Semiconductor ...
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... Transmit Buffer Time Stamp Register - Low Byte (CANTXFG_TSRL).......................................................459 13.4 Functional Description....................................................................................................................................................460 13.4.1 General.............................................................................................................................................................460 13.4.2 Message Storage..............................................................................................................................................461 13.4.2.1 Message Transmit Background......................................................................................................462 13.4.2.2 Transmit Structures........................................................................................................................462 13.4.2.3 Receive Structures..........................................................................................................................464 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Preliminary Page 21 ...
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... Wakeup Interrupt...........................................................................................................................479 13.4.7.5 Error Interrupt................................................................................................................................480 13.4.7.6 Interrupt Acknowledge..................................................................................................................480 13.4.7.7 Recovery from Stop or Wait..........................................................................................................480 13.5 Initialization Application Information............................................................................................................................481 13.5.1 MSCAN initialization......................................................................................................................................481 13.5.2 Bus-Off Recovery............................................................................................................................................481 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 22 Title Preliminary Page Freescale Semiconductor ...
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... IRQ Pending Register 1 (INTCIRQP1)...........................................................................................................504 14.2.18 IRQ Pending Register 2 (INTCIRQP2)...........................................................................................................505 14.2.19 IRQ Pending Register 3 (INTCIRQP3)...........................................................................................................505 14.2.20 IRQ Pending Register 4 (INTCIRQP4)...........................................................................................................506 14.2.21 Control Register (INTCCTRL)........................................................................................................................506 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 14 Interrupt Controller (INTC) Preliminary Page ...
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... OCCS External Clock Check Reference (OCCSCLKCHKR)........................................................................524 15.5.6 OCCS External Clock Check Target (OCCSCLKCHKT)..............................................................................525 15.5.7 OCCS Protection Register (OCCSPROT).......................................................................................................525 15.6 Functional Description....................................................................................................................................................526 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 24 Title Chapter 15 On-Chip Clock Synthesis (OCCS) Preliminary Page Freescale Semiconductor ...
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... Peripheral Clock Rate Register (SIMPCR)......................................................................................................547 16.2.12 Peripheral Clock Enable Register 0 (SIMPCE0).............................................................................................548 16.2.13 Peripheral Clock Enable Register 1 (SIMPCE1).............................................................................................549 16.2.14 Peripheral Clock Enable Register 2 (SIMPCE2).............................................................................................550 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 16 System Integration Module (SIM) Preliminary ...
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... Functional Description....................................................................................................................................................573 17.3 Memory Map and Registers............................................................................................................................................574 17.3.1 Power Supervisor Control Register (PSCTRL)...............................................................................................574 17.3.2 Power Supervisor Status Register (PSSTS).....................................................................................................575 17.4 Resets..............................................................................................................................................................................576 17.5 Clocks.............................................................................................................................................................................576 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 26 Title Chapter 17 Power Supervisor (PS) Preliminary Page Freescale Semiconductor ...
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... Modes of Operation ........................................................................................................................................587 19.1.3 Block Diagram ................................................................................................................................................588 19.2 External Signal Description ...........................................................................................................................................588 19.3 Memory Map and Registers............................................................................................................................................589 19.3.1 CRC High Register (CRCCRCH)....................................................................................................................589 19.3.2 CRC Low Register (CRCCRCL).....................................................................................................................590 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 18 Chapter 19 Preliminary Page 27 ...
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... Read Operation................................................................................................................................................610 20.3.2 Write Operation................................................................................................................................................610 20.3.3 Erase Operation................................................................................................................................................610 20.3.4 Flash Commands..............................................................................................................................................611 20.3.5 Set the Flash Program/Erase Clock (FCLK)....................................................................................................612 20.3.6 Command Sequence.........................................................................................................................................613 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 28 Title Chapter 20 Flash Memory (HFM) Preliminary Page Freescale Semiconductor ...
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... JTAG Port Architecture...................................................................................................................................623 21.4.2 Master TAP Instructions..................................................................................................................................623 21.4.2.1 Bypass Instruction (BYPASS).......................................................................................................624 21.4.2.2 IDCODE.........................................................................................................................................624 21.4.2.3 TLM_SEL......................................................................................................................................624 21.4.2.4 TAP Controller...............................................................................................................................625 21.5 Clocks.............................................................................................................................................................................627 21.6 Interrupts.........................................................................................................................................................................628 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Title Chapter 21 Preliminary Page 29 ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 30 Preliminary Freescale Semiconductor ...
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... It can be independently bulk erased or erased in pages. A comprehensive set of programmable peripherals—including a PWM, dual high-speed ADCs, queued SCIs, a queued SPI, I2Cs, an MSCAN, an inter-module Crossbar Switch, Quad Timers, a CRC block, DACs, analog comparators, and on-chip and off-chip clock MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary 31 ...
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... Dual clock sources • External crystal, resonator, external clock source • Internal 8 MHz/400 kHz relaxation oscillator • On-Chip Clock Synthesis (OCCS) module • On-chip Power Reset and Brown-Out Reset • On-chip low voltage detection MC56F825x/4x Reference Manual, Rev. 2, 10/2010 32 Preliminary Freescale Semiconductor ...
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... PWM, ADCs, Quad Timers, 12-bit DAC, HSCMPs, and package pins • general purpose I/O (GPIO) • tolerance • Configurable push-pull and open-drain output MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor TM placement; 520 ps PWM resolution Preliminary Chapter 1 Device Overview 33 ...
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... Each functional unit interfaces with the other units, memory, and the memory-mapped peripherals over the core's internal address and data buses, and through the IP bus bridge (off core). MC56F825x/4x Reference Manual, Rev. 2, 10/2010 34 Preliminary Freescale Semiconductor ...
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... GPIO port's peripheral enable register pin is multiplexed with different peripheral functions, control the selection of the peripheral function by using one of the GPIO peripheral select registers in the System Integration Module (SIM). MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor DSP56800E Core ALU1 Address Generation ...
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... GPIOB2 GPIOB1 GPIOB0 GPIOC15 GPIOC14 GPIOC13 GPIOC12 GPIOC11 GPIOC10 GPIOC9 GPIOC8 GPIOC7 GPIOC6 GPIOC5 GPIOC4 GPIOC3 GPIOC2 GPIOC1 GPIOC0 GPIOD3 GPIOD2 GPIOD1 GPIOD0 GPIOE7 GPIOE6 GPIOE5 GPIOE4 GPIOE3 GPIOE2 GPIOE1 GPIOE0 GPIOF7 GPIOF6 GPIOF5 GPIOF4 GPIOF3 GPIOF2 GPIOF1 GPIOF0 Freescale Semiconductor ...
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... When the external clock is chosen as the master clock source, its frequency should not exceed 60 MHz for the following cases: 1. The operation being performed is a flash programming/erase operation. 2. The CLKSRC bit of the MSCAN CANCTL1 register is set to 0. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor NOTE Preliminary Chapter 1 Device Overview 37 ...
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... Clock Generation and Distribution MC56F825x/4x Reference Manual, Rev. 2, 10/2010 38 Preliminary Freescale Semiconductor ...
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... In loop mode, the time between each conversion is 6 ADC clock cycles (600 ns). Using simultaneous conversion, two samples can be obtained in 600 ns. Samples per second is calculated according to 600 ns per two samples or 3,333,333 samples per second. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor 1 Preliminary 39 ...
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... Signed or unsigned result • Single-ended or differential inputs • PWM outputs with hysteresis for three of the analog inputs 2.1.3 Block Diagram The following figure illustrates the dual ADC configuration. Figure 2-1. Dual ADC Block Diagram MC56F825x/4x Reference Manual, Rev. 2, 10/2010 40 Preliminary Freescale Semiconductor ...
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... Sequential scans have access to all sixteen analog inputs. During parallel scans, each ADC converter has access to its eight analog inputs. An equivalent circuit for an analog input is shown below: MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Function Reset State ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 and V provides the reference voltage against REFH REFLO is nominally set to V REFH External Reference Voltage 0.1uF To ADC To ADC , measurements are made with respect to the amplitude of voltage is directly transferred to REFH Preliminary DDA REFLO REFH is as REFH Freescale Semiconductor ...
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... ADC_CLIST1 W R SAMPLE7 4 ADC_CLIST2 W R SAMPLE11 5 ADC_CLIST3 W R SAMPLE15 6 ADC_CLIST4 ADC_SDIS ADC_STAT W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor and V , are provided to reduce noise coupling and DDA SSA and V DDA SSA STAR CHNCFG_H STAR T1 ZCE6 ZCE5 ZCE4 SAMPLE2 SAMPLE6 SAMPLE10 ...
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... T F ADC_RSLT3 W SEX ADC_RSLT4 W SEX ADC_RSLT5 W SEX ADC_RSLT6 W SEX ADC_RSLT7 ADC_RSLT8 ADC_RSLT9 ADC_RSLT10 ADC_RSLT11 ADC_RSLT12 W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 RDY[15:0] HLS[7:0] 0 RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT RSLT Preliminary LLS[7:0] ZCS[7: Freescale Semiconductor 0 0 ...
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... ADC_LOLIM4 ADC_LOLIM5 ADC_LOLIM6 ADC_LOLIM7 ADC_HILIM0 ADC_HILIM1 ADC_HILIM2 ADC_HILIM3 ADC_HILIM4 ADC_HILIM5 W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor RSLT RSLT RSLT LLMT LLMT LLMT LLMT LLMT LLMT LLMT LLMT HLMT HLMT HLMT HLMT HLMT HLMT Preliminary Chapter 2 Analog-to-Digital Converter (ADC ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 HLMT HLMT OFFSET OFFSET OFFSET OFFSET OFFSET OFFSET OFFSET OFFSET 0 1 GAIN6 GAIN5 GAIN4 GAIN14 GAIN13 GAIN12 SC[15:0] 0 DIV1[4: Preliminary PUDELAY APD PD1 PD0 0 0 GAIN3 GAIN2 GAIN1 GAIN11 GAIN10 GAIN9 0 SPEEDB SPEEDA Freescale Semiconductor GAIN0 GAIN8 1 0 ...
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... SYNC inputs due to the SCTRL[SCn] bits. CTRL1[SYNC0] is cleared in ONCE mode, CTRL1[SMODE=000 or 001], when the first SYNC input is detected. This prevents unintentionally starting a new scan after the first scan has completed. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
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... Inputs = ANA2-ANA3 — Configured as differential pair (ANA2 is + and ANA3 is --) MC56F825x/4x Reference Manual, Rev. 2, 10/2010 48 Description and the - input and scale linearly between based on the REFLO REFH , and scale linearly between based on the amount REFLO . REFLO Table continues on the next page... Preliminary and the - input return REFH REFLO Freescale Semiconductor ...
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... While a loop is running, any additional start commands or sync pulses are ignored unless the scan is paused using the SCTRL[SC*] bits. When CTRL2[SIMULT (default), scanning restarts when either converter encounters a disabled sample. When CTRL2[SIMULT] is MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Sequential Versus Parallel Sampling Table continues on the next page ...
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... This is not the same as DSP STOP mode. 0 Normal operation 1 Stop mode 13 START1 Conversion START1 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 50 Description CHNCFG_H ADC_CTRL2 field descriptions Description Table continues on the next page... Preliminary DIV Freescale Semiconductor ...
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... Inputs = ANB4-ANB5 — Configured as differential pair (ANB4 is + and ANB5 is --) x0xx Inputs = ANB4-ANB5 — Both configured as single ended inputs MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description and the - input and scale linearly between based on the REFLO ...
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... ROSC Standby ROSC Normal 400kHz 8MHz 100K 2.00M 100K 1.00M 100K 667K 100K 500K 100K 400K 100K 333K - - 100K 62.5K Preliminary PLL 60 MHz External CLK 30.0M CLK/4 15.00M CLK/8 10.00M CLK/12 7.50M CLK/16 6.00M CLK/20 5.00M CLK/ 937K CLK/128 Freescale Semiconductor ...
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... Zero Crossing enabled for negative to positive sign change 11 Zero Crossing enabled for any sign change 5–4 Zero crossing enable 2 ZCE2 00 Zero Crossing disabled 01 Zero Crossing enabled for positive to negative sign change MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ZCE5 ZCE4 ZCE3 0 ...
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... Single Ended: ANA7, Differential: ANA6+, ANA7- 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- MC56F825x/4x Reference Manual, Rev. 2, 10/2010 54 Description SAMPLE2 SAMPLE1 ADC_CLIST1 field descriptions Description Table continues on the next page... Preliminary SAMPLE0 Freescale Semiconductor ...
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... Single Ended: ANA3, Differential: ANA2+, ANA3- 0100 Single Ended: ANB0, Differential: ANB0+, ANB1- 0101 Single Ended: ANB1, Differential: ANB0+, ANB1- 0110 Single Ended: ANB2, Differential: ANB2+, ANB3- MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Table continues on the next page... Preliminary 55 ...
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... Single Ended: ANB6, Differential: ANB6+, ANB7- 1110 Single Ended: ANB7, Differential: ANB6+, ANB7- 1111 11–8 Sample Field 6 SAMPLE6 Single Ended: ANA0, Differential: ANA0+, ANA1- 0000 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 56 Description SAMPLE6 SAMPLE5 ADC_CLIST2 field descriptions Description Table continues on the next page... Preliminary SAMPLE4 Freescale Semiconductor ...
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... Single Ended: ANA4, Differential: ANA4+, ANA5- 1001 Single Ended: ANA5, Differential: ANA4+, ANA5- 1010 Single Ended: ANA6, Differential: ANA6+, ANA7- 1011 Single Ended: ANA7, Differential: ANA6+, ANA7- MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Table continues on the next page... Preliminary 57 ...
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... Single Ended: ANA3, Differential: ANA2+, ANA3- 0011 Single Ended: ANB0, Differential: ANB0+, ANB1- 0100 Single Ended: ANB1, Differential: ANB0+, ANB1- 0101 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 58 Description SAMPLE10 SAMPLE9 ADC_CLIST3 field descriptions Description Table continues on the next page... Preliminary SAMPLE8 Freescale Semiconductor ...
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... Single Ended: ANB4, Differential: ANB4+, ANB5- 1100 Single Ended: ANB5, Differential: ANB4+, ANB5- 1101 1110 Single Ended: ANB6, Differential: ANB6+, ANB7- 1111 Single Ended: ANB7, Differential: ANB6+, ANB7- MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Preliminary 59 ...
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... Single Ended: ANA7, Differential: ANA6+, ANA7- 1011 Single Ended: ANB4, Differential: ANB4+, ANB5- 1100 Single Ended: ANB5, Differential: ANB4+, ANB5- 1101 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 SAMPLE14 SAMPLE13 ADC_CLIST4 field descriptions Description Table continues on the next page... Preliminary SAMPLE12 Freescale Semiconductor ...
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... Single Ended: ANB4, Differential: ANB4+, ANB5- 1100 Single Ended: ANB5, Differential: ANB4+, ANB5- 1101 Single Ended: ANB6, Differential: ANB6+, ANB7- 1110 Single Ended: ANB7, Differential: ANB6+, ANB7- 1111 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Preliminary 61 ...
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... Address: ADC_STAT – F080h base + 8h offset = F088h Bit EOSI EOSI Read CIP0 CIP1 0 1 Write Reset Field 15 Conversion in Progress CIP0 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 ADC_SDIS field descriptions Description LLMT HLMT ZCI ADC_STAT field descriptions Description Table continues on the next page... Preliminary UNDEFINED Freescale Semiconductor ...
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... This bit is cleared by writing a "1" to all active ZXSTAT[ZCS] bits zero crossing interrupt request 1 Zero crossing encountered, IRQ pending if CTRL1[ZCIE] is set 9 Low Limit Interrupt LLMTI MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Table continues on the next page... Preliminary 63 ...
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... The RDY[RDYn] bits are set as the individual channel conversions are completed. Polling the RDY[RDYn] bits can determine if a particular sample is ready to be read. 0 Sample not ready or has been read 1 Sample ready to be read MC56F825x/4x Reference Manual, Rev. 2, 10/2010 64 Description RDY[15: ADC_RDY field descriptions Description Preliminary Freescale Semiconductor ...
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... ADC Zero Crossing Status Register (ADC_ZXSTAT) Address: ADC_ZXSTAT – F080h base + Bh offset = F08Bh Bit Read 0 Write Reset Field 15–8 This read-only bitfield is reserved and always has the value zero. Reserved MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ADC_LIMSTAT field descriptions Description ...
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... ADC_RSLT4 – F080h base + 10h offset = F090h ADC_RSLT5 – F080h base + 11h offset = F091h ADC_RSLT6 – F080h base + 12h offset = F092h ADC_RSLT7 – F080h base + 13h offset = F093h Bit Read SEXT Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 66 Description Note RSLT Preliminary Freescale Semiconductor ...
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... ADC_RSLT12 – F080h base + 18h offset = F098h ADC_RSLT13 – F080h base + 19h offset = F099h ADC_RSLT14 – F080h base + 1Ah offset = F09Ah ADC_RSLT15 – F080h base + 1Bh offset = F09Bh Bit Read 0 Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ADC_RSLTn field descriptions Description Note RSLT Preliminary ...
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... This read-only bit is reserved and always has the value zero. Reserved 14–3 Low Limit Bits LLMT 2–0 This read-only bitfield is reserved and always has the value zero. Reserved MC56F825x/4x Reference Manual, Rev. 2, 10/2010 68 ADC_RSLTn field descriptions Description LLMT ADC_LOLIMn field descriptions Description Preliminary Freescale Semiconductor ...
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... The value of the offset register is used to correct the ADC result before it is stored in the RSLT registers. The offset value is subtracted from the ADC result. To obtain unsigned results, program the respective offset register with a value of $0000, thus giving a result range of $0000 to $7FF8. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
Page 70
... ADC module. Each converter and voltage reference generator have a manual power control bit capable of putting that component into the power down state. Converters have other mechanisms that can automatically put them into the power down state. Preliminary Freescale Semiconductor ...
Page 71
... This bit is asserted immediately following a write of "1" to PWR[PD1 de-asserted PWR[PUDELAY] ADC clock cycles after a write of "0" to PWR[PD1] if PWR[APD] is "0". This bit can be read as a status bit MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor The ADC module is idle when neither of the two converters has a scan in process. ...
Page 72
... Asserting this bit powers down converter B immediately. The results of a scan using converter B will be invalid while PWR[PD1] is asserted. When PWR[PD1] is cleared, converter B is either continuously powered up (PWR[APD automatically powered up when needed (PWR[APD]=1). MC56F825x/4x Reference Manual, Rev. 2, 10/2010 72 Description Table continues on the next page... Preliminary Freescale Semiconductor ...
Page 73
... Select V Source REFH SEL_VREFH_B This bit selects the source of the V 0 Internal VDDA 1 ANB2 14 Select V Source REFLO SEL_VREFLO_B This bit selects the source of the V MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Description ADC_CAL field descriptions Description reference for all conversions in converter 1. ...
Page 74
... Address: ADC_GC1 – F080h base + 36h offset = F0B6h Bit Read GAIN7 GAIN6 Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 74 Description reference for all conversions in converter 0. REFH reference for all conversions in converter 0. REFLO GAIN5 GAIN4 GAIN3 Preliminary GAIN2 GAIN1 GAIN0 Freescale Semiconductor ...
Page 75
... Gain Control Bit 2 GAIN2 GAIN 2 controls ANA2 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) ADC_GC1 field descriptions Description Table continues on the next page... Preliminary 75 ...
Page 76
... GAIN 15 controls ANA15 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved 13–12 Gain Control Bit 14 GAIN14 GAIN 14 controls ANA14 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 76 Description GAIN13 GAIN12 GAIN11 ADC_GC2 field descriptions Description Table continues on the next page... Preliminary GAIN10 GAIN9 GAIN8 Freescale Semiconductor ...
Page 77
... Gain Control Bit 9 GAIN9 GAIN 9 controls ANA9 00 x1 amplification 01 x2 amplification 10 x4 amplification 11 reserved 1–0 Gain Control Bit 8 GAIN8 GAIN 8 controls ANA8 00 x1 amplification MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Table continues on the next page... Preliminary 77 ...
Page 78
... Address: ADC_SCTRL – F080h base + 38h offset = F0B8h Bit Read Write Reset Field 15–0 Scan Control Bits SC[15:0] 0 Perform sample immediately after the completion of the current sample. 1 Delay sample until a new sync input occurs. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 78 Description SC[15: ADC_SCTRL field descriptions Description Preliminary Freescale Semiconductor ...
Page 79
... The ADC consists of two eight-channel input select functions, which are two independent sample and hold (S/H) circuits feeding two separate 12-bit ADCs. The two separate converters store their results in an accessible buffer, awaiting further processing. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
Page 80
... Converter A can sample only analog inputs ANA[0:7], and converter B can sample only analog inputs ANB[0:7]. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 80 A/D 0 A/D 1 Preliminary ADRSLT0 ADRSLT1 ADRSLT2 ADRSLT3 ADRSLT4 ADRSLT5 ADRSLT6 ADRSLT7 ADRSLT8 ADRSLT9 ADRSLT10 ADRSLT11 ADRSLT12 ADRSLT13 ADRSLT14 ADRSLT15 Freescale Semiconductor ...
Page 81
... Scanning in both converters terminates when either converter encounters a disabled sample. In non-simultaneous scan mode, the parallel scans in the two converters occur MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) SAMPLEn is from ADLST1 or ADLST3. SAMPLEm is from ADLST2 or ADLST4. ...
Page 82
... The following figure shows the input multiplex function. The ChannelSelect and SingleEndedDifferential switches are indirectly controlled by settings within the following registers: • CLIST1, CLIST2, CLIST3, CLIST4, and SDIS registers • CTRL1[CHNCFG_L] • CTRL2[CHNCFG_H] MC56F825x/4x Reference Manual, Rev. 2, 10/2010 82 Preliminary Freescale Semiconductor ...
Page 83
... ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 (Vrefh + Vrefl)/2 The multiplexing for conversions in different operating modes is as follows: MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Channel Select Single-Ended Differential Channel Select Single-Ended Differential Figure 2-69. Input Select Multiplex Preliminary Chapter 2 Analog-to-Digital Converter (ADC) ...
Page 84
... A/D. The lower switch is closed, provid‐ ing the differential input of REF the A/D. The upper switch is always closed so that any of the four inputs can get to the A/D input. Freescale Semiconductor ...
Page 85
... Each sub-ranging section runs at a maximum clock speed of 10 MHz complete 12-bit conversion can be accommodated in 600 ns, not including sample or post-processing time. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Channel Select Switches The channel select switches are turned on in pairs, providing a dual 1-of-4 select function so that either of the two differential channels can be routed to the A/D input ...
Page 86
... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 86 Interface Function/ Multiplex Program Gain θ θ Interface Function/ Multiplex Program Gain reference. The ADC measures REFLO Preliminary RSD 1 RSD 2 θ θ 1 Cyclic ADC Core Converter A RSD 1 RSD 2 θ 1 θ Cyclic ADC Core Converter B - REFH –V ) REFH REFLO Freescale Semiconductor ...
Page 87
... Note: The ADC is a 12-bit function with 4096 possible states. However, the 12 bits have been left shifted three bits on the 16-bit data bus, so the magnitude of this function, as read from the data bus, is now 32760. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor - V )/( × ...
Page 88
... RSLT5 as if the analog core had provided the data. This test data must be justified, as illustrated by the RSLT register definition and does not include the sign bit. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 88 Note: Normally, VREFLO is set to VSSA = 0 V. AN+ AN– AN+ AN– REF + V )/2. REFH REFLO Preliminary Freescale Semiconductor ...
Page 89
... STAT[EOSI0] interrupt if the CTRL1[EOSIEN0] interrupt enable is set. The CTRL1[START0] bit and SYNC0 input are ignored while a scan is in process. Scanning stops and cannot be initiated when the CTRL1 [STOP0] bit is set. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Preliminary 89 ...
Page 90
... CTRL*[SYNC*] bits is not necessary. • Looping scan. Automatically restarts a scan, either parallel or sequential, as soon as the previous scan completes. In parallel looping scan modes, the A converter scan restarts as soon as the A converter scan completes and the B converter scan restarts MC56F825x/4x Reference Manual, Rev. 2, 10/2010 90 Preliminary Freescale Semiconductor ...
Page 91
... Auto-standby is a compromise between normal and auto-powerdown modes. This mode offers moderate power savings at the cost of a moderate latency when leaving the idle state to start a new scan. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Description Table continues on the next page... ...
Page 92
... Clear the PWR[PD0 and/or PD1] bits to power up the required converters. 4. Poll the status bits until all required converters are powered up. 5. Start scan operations. This will provide a full power-up delay before scans begin. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 92 Description Preliminary Freescale Semiconductor ...
Page 93
... Any write to the result register in the ADC-STOP mode is treated as if the analog core supplied the data, so limit checking and zero crossing and associated interrupts can occur if enabled. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Preliminary 93 ...
Page 94
... Maximum rate is 60 MHz. When the PLL is on and selected PLL out‐ put divided by 4. When PLL is not selected MSTR_OSC/2. When the device is in low-power mode, ROSB=1, the rate is 200 kHz. ROSC provides 8 MHz for auto-standby power saving mode. Preliminary Freescale Semiconductor ...
Page 95
... It is derived by multiplexing the conversion clock (divided version of the conversion clock source) and the standby clock (divided version of MSTR_OSC). This clock can be selected in the SIM for external output for debug and failure analysis. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor IP_CLK Divide By 2(DIV + 1) ...
Page 96
... Zero Crossing, low Limit, and high limit interrupt Conversion Complete Interrupt for any scan type except converter B scan in non-simultaneous parallel scan mode (see EOSI0) Conversion Complete Interrupt for converter B scan in non-simultane‐ ous parallel scan mode (see EOSI1) Preliminary Freescale Semiconductor ...
Page 97
... When the PWR[APD or ASB] bit is set, the sync pulse or start powers up the ADC, waits for a number of ADC clocks (determined by the PWR[PUDELAY] bits) for the ADC circuitry to stabilize, and only then begins the conversion sequence. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 2 Analog-to-Digital Converter (ADC) Ignored sample0 Figure 2-74 ...
Page 98
... Timing Specifications MC56F825x/4x Reference Manual, Rev. 2, 10/2010 98 Preliminary Freescale Semiconductor ...
Page 99
... Comparator output may be: • Sampled • Windowed (ideal for certain PWM zero-crossing-detection applications) • Digitally filtered: • Filter can be bypassed. • May be clocked through the external SAMPLE signal or a scaled peripheral clock. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary 99 ...
Page 100
... Internal Bus FILT_PER FILTER_CNT INV WE COS Window Polarity Control Select ACO Window/Sample 1 1 Clock 0 0 Prescaler Divided CGMUX Peripheral Clock SE Preliminary OPE SE COUT IER/F CFR/F Filter Interrupt Block Control IRQ COUT (To Other DSC Functions) 0 COUTA CMPO to 1 Pad COS Freescale Semiconductor ...
Page 101
... Consult the data sheet to determine what functions are shared with analog inputs. As shown in the block diagram, the Pn pins are connected to the comparator non-inverting input. Mn pins are connected to the inverting input of the comparator. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 3 High Speed Comparator (HSCMP) OR AND ...
Page 102
... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 102 Alt Function 1 Alternate Pin Owner 1 Alt Function n Alternate Pin Owner Explicit Multiplexing Controls Figure 3-3. OPE Operation Preliminary Explicit I/O Multiplexing I/O Pad FILTER_CNT PMC INV COS OPE EN FILT_PER HYST_SEL IER IEF CFR CFF Freescale Semiconductor 0 MMC 0 ...
Page 103
... CMPB_CR0 – F1C0h base + 0h offset = F1C0h CMPC_CR0 – F1D0h base + 0h offset = F1D0h Bit Read Write Reset Field 15–7 This read-only bitfield is reserved and always has the value zero. Reserved 6–4 Filter Sample Count FILTER_CNT MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
Page 104
... CMPC_CR1 – F1D0h base + 1h offset = F1D1h Bit Read 0 Write Reset Field 15–8 This read-only bitfield is reserved and always has the value zero. Reserved MC56F825x/4x Reference Manual, Rev. 2, 10/2010 104 Description CMPx_CR1 field descriptions Description Table continues on the next page... Preliminary INV COS OPE Freescale Semiconductor ...
Page 105
... Comparator Module Enable EN The EN bit enables the Analog Comparator Module. When the module is not enabled, it remains in the off state, and consumes no power. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 3 High Speed Comparator (HSCMP) Description Table continues on the next page... Preliminary ...
Page 106
... See the tONEN, tONPOR, and tONPPD electrical specifications in the data sheet. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 106 Description CMPx_FPR field descriptions Description NOTE Preliminary FILT_PER Freescale Semiconductor ...
Page 107
... STOP modes. If the CFF and CFR flags are to be active during STOP, then SMELB must be set to “0” for cases where the it is not receiving a clock during STOP. 0 Rising edge on COMPO has not been detected. 1 Rising edge on COUT has occurred. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
Page 108
... In the simplest case, only one sample must agree, and the filter acts as a simple sampler. The external sample input is enabled using the CR1[SE] bit. When this bit is set, the output of the comparator is sampled only on rising edges of the sample input. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 108 Description Preliminary Freescale Semiconductor ...
Page 109
... PWM fault circuitry. Filtering and sampling settings should be changed only after setting and FILTER_CNT to 0x0. These values have the effect of resetting the filter to a known state. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 3 High Speed Comparator (HSCMP) Disabled X X ...
Page 110
... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 110 Internal Bus FILT_PER FILTER_CNT COS INV Window Polarity Control - Select ACO Windows/Sample 1 0 Clock Prescaler Divided Peripheral CGMUX Clock SE Preliminary OPE SE COUT IER/F CFR/F Filter Interrupt Control Block IRQ COUT (To Other DSC Functions) 0 COUTA 1 CMPO to Pad COS Freescale Semiconductor ...
Page 111
... The only difference in operation between Sampled, Non-Filtered (3A) and Sampled, Non-Filtered (3B how the clock to the filter block is derived. The comparator filter has no other function than sample/hold of the comparator output in this mode. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Internal Bus FILT_PER FILTER_CNT COS ...
Page 112
... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 112 Internal Bus FILT_PER FILTER_CNT COS INV Window Polarity Control Select Window/Sample 1 Clock 0 Prescaler Divided CGMUX Peripheral Clock SE=0 Preliminary OPE SE COUT IER/F CFR/F 1 Interrupt Filter Control Block IRQ COUT (To Other DSC Functions CMPO to Pad COS Freescale Semiconductor ...
Page 113
... PMC[1:0] MMC[1:0] EN, PMODE Peripheral Clock FILT_PER Figure 3-23. Sampled, Filtered (4A): Sampling Point Externally Driven MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Internal Bus FILT_PER FILTER_CNT COS INV WE 0 >0x1 Window Polarity Control Select ACO Window/Sample 1 Clock 0 Prescaler CGMUX Preliminary Chapter 3 High Speed Comparator (HSCMP) ...
Page 114
... Internal Bus FILT_PER FILTER_CNT SE COS INV WE 0 >0x1 Window Polarity Control Select ACO Window/Sample 1 Clock 0 Prescaler Divided CGMUX Peripheral Clock Preliminary OPE COUT IER/F CFR/F 1 Filter Interrupt Block Control IRQ COUT (To Other DSC Functions) 0 COUTA CMPO to 1 Pad COS Freescale Semiconductor ...
Page 115
... EN, PMODE Peripheral Clock FILT_PER When any windowed mode is active, COUTA is clocked by the peripheral clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Internal Bus FILT_PER FILTER_CNT COS INV WE + Window Polarity Control - Select Window/Sample ...
Page 116
... FILT_PER and the peripheral clock rate. Configuration for this mode is virtually identical to that for the windowed/filtered mode shown in the next section. The only difference is that the value of FILTER_CNT must be exactly one. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 116 Preliminary Freescale Semiconductor ...
Page 117
... Figure 3-28. Windowed/Filtered Mode 3.6.2 Power Modes The following table summarizes the terms that apply for each power mode. Table 3-22. Freescale Power Modes Power Mode Comments Run Normal operating mode MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Internal Bus FILT_PER FILTER_CNT COS INV ...
Page 118
... Because positive feedback is required, INV must be set to 0 when the hysteresis resistor bridge is added to the positive (+) input of the comparator. INV must be set to 1 when the hysteresis resistor bridge is added to the negative (–) input of the comparator. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 118 Preliminary Freescale Semiconductor ...
Page 119
... Filter delay is specified in the Low-Pass Filter section. Interrupts should be disabled during power up, recovery from partial-power-down, and while re-enabling the module. Failure could result in spurious interrupts. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 3 High Speed Comparator (HSCMP) COUTA CMPO COS ...
Page 120
... The filter output is at zero when first initialized and subsequently changes when the FILTER_CNT field's consecutive samples all agree that the output value has changed. Said another way, COUT is zero for some initial period, even when COUTA is at one. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 120 Preliminary Freescale Semiconductor ...
Page 121
... X MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 3 High Speed Comparator (HSCMP) Operation Disabled X X Continuous Mode 0x00 X Sampled, Non- Filtered mode > 0x0 X T Sampled, Fil‐ PD tered mode > 0x0 T + (FILTER_CNT X FILT_PER Windowed mode 0x00 Table continues on the next page... ...
Page 122
... SCR[CFF] bits for a falling-edge interrupt. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 122 Operation 0x01 - Windowed / Re‐ T 0xFF sampled mode 0x01 - Windowed / Fil‐ (FILTER_CNT X FILT_PER 0xFF tered mode Preliminary 1 Maximum Latency + (FILT_PER per per ) + per 2T per is the clock period of the SAMPLE Freescale Semiconductor ...
Page 123
... Output that is internally routed to internal analog comparator positive input 0 • 5bDACAO is internally routed to CMPA_P0 • 5bDACBO is internally routed to CMPB_P0 • 5bDACCO is internally routed to CMPC_P0 • Ability to remain operating in STOP mode MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor into 32 voltage levels. A 5-bit digital signal DDA to V DDA Preliminary /32 ...
Page 124
... Memory Map and Registers Address Register offset (hex) name 15 R REFA_ 0 DACCTRL W R REFB_ 0 DACCTRL W R REFC_ 0 DACCTRL W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 124 VOSEL[4:0] DDA DACnO SSA Figure 4-1. DAC Block Diagram Preliminary DACEN VOSEL 0 0 VOSEL 0 0 VOSEL Freescale Semiconductor 0 0 ...
Page 125
... When the module is disabled, its output, DACO, should be equal to (is connected to the positive input 0 of one of the comparators. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 4 5-Bit Voltage Reference Digital-to-Analog Converter (VREF_DAC ...
Page 126
... Resets This module has a single reset input, which corresponds to the device-wide peripheral reset. 4.5 Clocks This module has a single clock input: the bus peripheral clock. 4.6 Interrupts This module has no interrupts. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 126 Preliminary Freescale Semiconductor ...
Page 127
... Automatic mode to generate square, triangle, and sawtooth output waveforms • Automatic mode to allow programmable period, update rate, and range • Support of two digital formats • Glitch filter to suppress output glitch during data conversion MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary 127 ...
Page 128
... R FILT_CNT 0 DAC_CTRL W R DAC_DATA 1 [FORMAT= DAC_DATA 1 [FORMAT= MC56F825x/4x Reference Manual, Rev. 2, 10/2010 128 Automatic Waveform Generation 1 12 Data Data 0 Format Register VDD AUTO 0 Update 1 Figure 5-1. DAC Block Diagram DATA Preliminary PDN DAC Analog Output 0 Filter 1 FILT_EN DATA Freescale Semiconductor 0 0 ...
Page 129
... NOTE: When using the glitch filter be sure that the filter count is less than the update count otherwise the DAC output will never be updated. 12 Glitch Filter Enable FILT_EN This bit enables the glitch suppression filter. This introduces a latency based on CTRL[FILT_CNT] for DAC updates. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC ...
Page 130
... Two data formats can be used for the DAC. When this bit is clear, the 12 bits of data are right justified within the 16 bit DATA register. When this bit is set, the 12 bits of data are left justified. In either case the 4 unused bits are ignored. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 130 Description Table continues on the next page... Preliminary Freescale Semiconductor ...
Page 131
... The data in this buffer can be updated at any rate, but the DAC output load impedance may affect the updating rate. 5.2.3 Buffered Data Register (DAC_DATA [FORMAT=1]) Address: DAC_DATA [FORMAT=1] – F1A0h base + 1h offset = F1A1h Bit Read Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC) Description Description 11 ...
Page 132
... Step Size Register (DAC_STEP [FORMAT=1]) Address: DAC_STEP [FORMAT=1] – F1A0h base + 2h offset = F1A2h Bit Read Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 132 Description Description STEP Preliminary STEP Freescale Semiconductor ...
Page 133
... NOTE: If DAC input data is less than MINVAL, output will be limited to MINVAL during automatic waveform generation. 5.2.7 Minimum Value Register (DAC_MINVAL [FORMAT=1]) Address: DAC_MINVAL [FORMAT=1] – F1A0h base + 3h offset = F1A3h Bit Read Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC) Description MINVAL Description ...
Page 134
... Please refer to the chip data sheet for limitations on the high end voltage output of the DAC. NOTE: If DAC input data is greater than MAXVAL, output will be limited to MAXVAL during automatic waveform generation. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 134 Description MAXVAL Description Preliminary Freescale Semiconductor ...
Page 135
... This DAC supports two conversion modes: asynchronous conversion and synchronous conversion. 5.3.1.1 Asynchronous conversion mode Data can be immediately presented to the DAC and converted to an analog output when it is written to the DAC buffered data register. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC ...
Page 136
... The generator starts subtracting STEP from DATA if CTRL[DOWN] is set (down counting enabled) or reloading MINVAL if CTRL[DOWN] is clear (no down counting). 5. When DATA reaches MINVAL while counting down, the generator starts counting up if CTRL[UP] is set or reloads MAXVAL if CTRL[UP] is clear (up counting disabled). MC56F825x/4x Reference Manual, Rev. 2, 10/2010 136 Preliminary Freescale Semiconductor ...
Page 137
... MINVAL VSS SYNC_IN Figure 5-11. Sawtooth Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=0 VDD MAXVAL STEP MINVAL VSS SYNC_IN Figure 5-12. Triangle Waveform Example with CTRL[UP]=1 and CTRL[DOWN]=1 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC) Preliminary 137 ...
Page 138
... The maximum settling time will not exceed 2 microseconds with a maximum output load (3 kohm || 400 pf) when the output swings from minimum output to maximum output or vice-versa. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 138 Preliminary Freescale Semiconductor ...
Page 139
... CTRL[FILT_CNT] a suitable value to cause the DAC to hold its current output for a number of clock cycles equal CTRL[FILT_CNT while the switching glitches settle out. After the filter time is satisfied, the output smoothly slews to the new value. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC) Preliminary 139 ...
Page 140
... Another form of clipping occurs when the MAXVAL or MINVAL is beyond the output range of the DAC. The maximum and minimum voltages that can be driven out are defined in the device data sheet. 5.4 Resets When reset, all of the registers return to the reset state. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 140 Clipped Step Preliminary Freescale Semiconductor ...
Page 141
... Clocks The DAC uses the system bus clock (IPBus clock). 5.6 Interrupts The DAC module does not generate any interrupts. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 5 12-Bit Digital-to-Analog Converter (DAC) Preliminary 141 ...
Page 142
... Interrupts MC56F825x/4x Reference Manual, Rev. 2, 10/2010 142 Preliminary Freescale Semiconductor ...
Page 143
... The prescaler provides different time bases useful for clocking the counter/timer. The counter provides the ability to count internal or external events. Within a timer module (set of four timer/counters), the input pins are shareable. 6.2 Features The TMR module design includes these distinctive features: MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary 143 ...
Page 144
... The TMR module design operates in only a single mode of operation: Functional Mode. The various counting modes are detailed in the Functional Description. 6.4 Block Diagram Each of the timer/counter groups within the quad-timer are shown in this figure. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 144 Preliminary Freescale Semiconductor ...
Page 145
... Make certain to check which quad timer is available on the chip being used, and which timer channels have external I/O. Address Register offset (hex) name 15 R TMRA0_ 0 COMP1 W R TMRA0_ 1 COMP2 TMRA0_CAPT TMRA0_LOAD W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor COMPARISON_1 COMPARISON_2 CAPTURE LOAD Preliminary Chapter 6 Quad Timer (TMR ...
Page 146
... W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 146 HOLD COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS Preliminary DIR OUTMODE 0 VAL OPS FORC E CL2 CL1 FILT_PER ENBL DIR OUTMODE Freescale Semiconductor 0 0 ...
Page 147
... TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL W R TMRA2_ TCF 7 SCTRL W R TMRA2_ 8 CMPLD1 W R TMRA2_ 9 CMPLD2 W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 ...
Page 148
... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 148 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 Preliminary CL2 CL1 FILT_PER RSVD DIR OUTMODE 0 VAL OPS FORC E CL2 CL1 FILT_PER RSVD Freescale Semiconductor 0 0 ...
Page 149
... R B TMRB0_FILT TMRB0_ENBL W R TMRB1_ 0 COMP1 W R TMRB1_ 1 COMP2 TMRB1_CAPT TMRB1_LOAD TMRB1_HOLD W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD 14 13 ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 150 COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS TOF IEF IPS Preliminary DIR OUTMODE 0 VAL OPS FORC E CL2 CL1 FILT_PER RSVD DIR OUTMODE 0 VAL OPS FORC Freescale Semiconductor 0 0 ...
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... W R TMRB3_ TCF 7 SCTRL W R TMRB3_ 8 CMPLD1 W R TMRB3_ 9 CMPLD2 W R TMRB3_ DBG_EN A CSCTRL TMRB3_FILT W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 UP 0 TCI 0 FILT_CNT 0 COMPARISON_1 COMPARISON_2 CAPTURE LOAD HOLD COUNTER PCS SCS TOF IEF IPS COMPARATOR_LOAD_1 COMPARATOR_LOAD_2 ...
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... TMRB3_COMP1 – F070h base + 0h offset = F070h Bit Read Write Reset Field 15–0 Comparison Value 1 COMPARISON_ This read/write register stores the value used for comparison with the counter value. 1 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 152 COMPARISON_1 TMRx_COMP1 field descriptions Description Preliminary RSVD Freescale Semiconductor ...
Page 153
... TMRB0_CAPT – F040h base + 2h offset = F042h TMRB1_CAPT – F050h base + 2h offset = F052h TMRB2_CAPT – F060h base + 2h offset = F062h TMRB3_CAPT – F070h base + 2h offset = F072h Bit Read Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor COMPARISON_2 TMRx_COMP2 field descriptions Description 11 10 ...
Page 154
... TMRB3_LOAD – F070h base + 3h offset = F073h Bit Read Write Reset Field 15–0 Timer Load Register LOAD This read/write register stores the value used to initialize the counter. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 154 TMRx_CAPT field descriptions Description LOAD TMRx_LOAD field descriptions Description Preliminary Freescale Semiconductor ...
Page 155
... TMRB0_CNTR – F040h base + 5h offset = F045h TMRB1_CNTR – F050h base + 5h offset = F055h TMRB2_CNTR – F060h base + 5h offset = F065h TMRB3_CNTR – F070h base + 5h offset = F075h Bit Read Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor HOLD TMRx_HOLD field descriptions Description 11 10 ...
Page 156
... NOTE: A timer selecting its own output for input is not a legal choice. The result is no counting. 0000 Counter 0 input pin 0001 Counter 1 input pin MC56F825x/4x Reference Manual, Rev. 2, 10/2010 156 TMRx_CNTR field descriptions Description PCS SCS TMRx_CTRL field descriptions Description Table continues on the next page... Preliminary DIR OUTMODE Freescale Semiconductor ...
Page 157
... For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on. 4 Count Direction DIR MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Description Table continues on the next page... Preliminary Chapter 6 Quad Timer (TMR) 157 ...
Page 158
... TMRB1_SCTRL – F050h base + 7h offset = F057h TMRB2_SCTRL – F060h base + 7h offset = F067h TMRB3_SCTRL – F070h base + 7h offset = F077h Bit Read TOFI TCF TOF E Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 158 Description INPU CAPTURE_ T IEF IEFIE IPS MODE Preliminary EEOF VAL OPS OEN FORCE Freescale Semiconductor ...
Page 159
... OFLAG output signal. 3 Forced OFLAG Value VAL This bit determines the value of the OFLAG output signal when software triggers a FORCE command. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor TMRx_SCTRL field descriptions Description Table continues on the next page... Preliminary Chapter 6 Quad Timer (TMR) ...
Page 160
... Read Write Reset Field 15–0 This read/write register is the comparator 1 preload value for the COMP1 register for the corresponding COMPARATOR_ channel in a timer module. LOAD_1 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 160 Description COMPARATOR_LOAD_1 TMRx_CMPLD1 field descriptions Description Preliminary Freescale Semiconductor ...
Page 161
... TMRB0_CSCTRL – F040h base + Ah offset = F04Ah TMRB1_CSCTRL – F050h base + Ah offset = F05Ah TMRB2_CSCTRL – F060h base + Ah offset = F06Ah TMRB3_CSCTRL – F070h base + Ah offset = F07Ah Bit Read DBG_EN ROC Write Reset MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor COMPARATOR_LOAD_2 TMRx_CMPLD2 field descriptions Description ...
Page 162
... The last count was in the DOWN direction. 1 The last count was in the UP direction. 8 This read-only bit is reserved and always has the value zero. Reserved MC56F825x/4x Reference Manual, Rev. 2, 10/2010 162 TMRx_CSCTRL field descriptions Description Table continues on the next page... Preliminary Freescale Semiconductor ...
Page 163
... The values of FILT_PER and FILT_CNT must also be balanced against the desire for minimal latency in recognizing input transitions. Turning on the input filter (setting FILT_PER to a non-zero value) introduces a latency of (((FILT_CNT + 3) x FILT_PER bus clock periods. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Description Preliminary Chapter 6 Quad Timer (TMR) 163 ...
Page 164
... The value of FILT_PER affects the input latency. When changing values for FILT_PER from one non-zero value to another non-zero value, write a value of zero first to clear the filter. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 164 FILT_CNT TMRx_FILT field descriptions Description Preliminary FILT_PER Freescale Semiconductor ...
Page 165
... The counter can count the rising, falling, or both edges of the selected input pin. • The counter can decode and count quadrature encoded input signals. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor ...
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... Any counter/timer can be assigned as a master. A master's compare signal can be broadcast to the other counter/timers within the module. The other counters can be configured to reinitialize their counters and/or force their OFLAG output signals to predetermined values when a master's counter/timer compare event occurs. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 166 Preliminary Freescale Semiconductor ...
Page 167
... This example uses TMRA1 to count pulse (actually counts rising edges of the pulse) // from an external source (TA3). // void Pulse_Init(void TMRA1_CTRL: CM=0,PCS=3,SCS=0,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */ setReg(TMRA1_CTRL,0x0600); /* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */ setReg(TMRA1_SCTRL,0x00); setReg(TMRA1_CNTR,0x00); setReg(TMRA1_LOAD,0x00); setRegBitGroup(TMRA1_CTRL,CM,0x01); } MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Run counter */ Preliminary Chapter 6 Quad Timer (TMR) 167 ...
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... Example: 6.6.2.3.1 Count Both Edges of External Source Signal MC56F825x/4x Reference Manual, Rev. 2, 10/2010 168 /* Stop all functions of the timer */ /* Reset load register */ /* Set up compare 1 register */ /* Also set the compare preload register */ /* Enable compare 1 interrupt and */ /* compare 1 preload */ /* Reset counter register */ Preliminary Freescale Semiconductor ...
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... TMRA1_CTRL: CM=0,PCS=8,SCS=1,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */ setReg(TMRA1_CTRL,0x1080); /* TMRA1_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */ setReg(TMRA1_SCTRL,0x00); setReg(TMRA1_CNTR,0x00); setReg(TMRA1_LOAD,0x00); setRegBitGroup(TMRA1_CTRL,CM,0x03); } > MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Run counter */ /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Run counter */ Preliminary Chapter 6 Quad Timer (TMR) ...
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... TMRA0_SCTRL: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0, Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */ setReg(TMRA0_SCTRL,0x00); setReg(TMRA0_CNTR,0x00); setReg(TMRA0_LOAD,0x00); setReg(TMRA0_COMP1,0xFFFF); setReg(TMRA0_COMP2,0x00); /* TMRA0_CSCTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0, TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */ setReg(TMRA0_CSCTRL,0x00); setRegBitGroup(TMRA0_CTRL,CM,0x04); } > MC56F825x/4x Reference Manual, Rev. 2, 10/2010 170 + Set up mode */ /* Reset counter register */ /* Reset load register */ /* Set up compare 1 register */ /* Set up compare 2 register */ /* Run counter */ Preliminary - Freescale Semiconductor ...
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... Signed-Count Mode If CTRL[CM] is set to '101', the counter counts the primary clock source while the selected secondary source provides the selected count direction (up/down). MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Set up compare 1 register */ ...
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... Primary Secondary Count 12 13 timer_out Figure 6-120. Triggered Count Mode 1 (CTRL[LENGTH]=0) Example: 6.6.2.8.1 Triggered Count Mode 1 Example MC56F825x/4x Reference Manual, Rev. 2, 10/2010 172 /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Run counter */ COMP1 = 18 Preliminary 18 17 Freescale Semiconductor ...
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... Count Secondary Figure 6-121. Triggered Count Mode 2 (CTRL[LENGTH]=0) Example: 6.6.2.9.1 Triggered Count Mode 2Example MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Set up compare 1 register */ /* Run counter */ ...
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... Primary Secondary Count 0 1 timer_out Figure 6-122. One-Shot Mode (CTRL[LENGTH]=1) Example: 6.6.2.10.1 One-Shot Mode Example MC56F825x/4x Reference Manual, Rev. 2, 10/2010 174 /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Set up compare 1 register */ LOAD = 0, COMP1 = 4 Preliminary Freescale Semiconductor ...
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... First read any counter of a cascaded counter chain, then read the hold registers of the other counters in the chain. The cascaded counter mode is synchronous. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Set up mode */ /* Reset counter register */ /* Reset load register */ ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 176 Note /* Stop all functions of the timer */ /* Set up cascade counter mode */ /* Reset counter register */ /* Reset load register */ /* milliseconds in 30 seconds */ // Set to cycle every milisecond /* Enable compare 1 interrupt and */ /* compare 1 preload /* Enable Compare 1 preload */ /* Run counter */ Preliminary */ Freescale Semiconductor ...
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... This mode is useful for driving step motor systems. This does not work if CTRL[PCS] is set to 1000 (IP_bus/1). Example: 6.6.2.12.1 Pulse Outputs Using Two Counters MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Note Figure 6-123. Pulse Output Mode Preliminary Chapter 6 Quad Timer (TMR) ...
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... MC56F825x/4x Reference Manual, Rev. 2, 10/2010 178 /* Set up mode */ /* Reset load register */ /* (16 * 37500 ) / 60e6 = 0.01 sec */ /* Set up comparator control register */ /* Set up mode */ /* Reset counter register */ /* Reset load register */ /* Set up compare 1 register */ /* Set up comparator control register */ /* Reset counter */ /* Run source clock counter */ /* Run counter */ Preliminary Freescale Semiconductor ...
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... CM=3'b001 (count rising edges of primary source) • PCS=4'b1000 (IP bus clock for best granularity for waveform timing) • SCS=Any (ignored in this mode) MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor /* Reset counter */ /* Enable output */ /* Store initial value to the duty-compare register */ /* Run counter */ ...
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... Additionally the user will need to write an interrupt service routine minimum the following: • Clear CSCTRL[TCF2] and CSCTRL[TCF1] flags. • Calculate and write new values for both CMPLD1 and CMPLD2. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 180 Preliminary Freescale Semiconductor ...
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... CSCTRL[TCF1] is asserted. One clock later, OFLAG toggles, CMPLD2 is copied to COMP2, LOAD is copied to CNTR and the counter starts counting. Step 5-- The counter continues counting until CNTR matches COMP2. Figure 6-124. Compare Load Timing MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Compare Preload Cycle Step 2 Step 3 Step 4 c2 ...
Page 182
... Set Comparator Status and Control Register */ /* Set the pulse width of the off time */ /* Set the pulse width of the off time */ /* Set the pulse width of the on time */ /* Set the pulse width of the on time */ /* Set variable PWM mode and run counter */ Preliminary Freescale Semiconductor ...
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... COMP2 determines the pulse width for the logic high part of OFLAG. The period of the waveform is determined by the COMP1 and COMP2 values and the frequency of the primary clock source. See the following figure. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary Chapter 6 Quad Timer (TMR) 183 ...
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... OFLAG signal asserted. The counter will be turned off until the settings in the control register are changed. Reset Priority RST_B n/a MC56F825x/4x Reference Manual, Rev. 2, 10/2010 184 COMP2 PWM Period Table 6-127. Reset Summary Source Characteristics Hardware Reset Full System Reset Preliminary Freescale Semiconductor ...
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... TMR Channel 2 TMR2_COMP2_IRQ_B Compare 2 Interrupt Request for Timer Channel 2 TMR2_OVF_IRQ_B TMR2_EDGE_IRQ_B MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Table 6-128. Interrupt Summary Description Overflow Interrupt Request for Timer Channel 0 Input Edge Interrupt Request for Timer Channel 0 Overflow Interrupt Request for Timer Channel 1 ...
Page 186
... These interrupts are generated when a counter rolls over its maximum value while SCTRL[TOFIE] is set. These interrupts are cleared by writing zero to the appropriate SCTRL[TOF]. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 186 Description Overflow Interrupt Request for Timer Channel 3 Input Edge Interrupt Request for Timer Channel 3 Preliminary Freescale Semiconductor ...
Page 187
... Timer Input Edge Interrupts These interrupts are generated by a transition of the input signal (either positive or negative depending on IPS setting) while SCTRL[IEFIE] is set. These interrupts are cleared by writing a zero to the appropriate SCTRL[IEF]. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary Chapter 6 Quad Timer (TMR) 187 ...
Page 188
... Description of Interrupt Operation MC56F825x/4x Reference Manual, Rev. 2, 10/2010 188 Preliminary Freescale Semiconductor ...
Page 189
... Independently programmable PWM output polarity • Independent top and bottom deadtime insertion • Each complementary pair can operate with its own PWM frequency and deadtime values • Individual software control for each PWM output MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Preliminary 189 ...
Page 190
... The following table identifies PWM feature support that varies by submodule (SM). Table 7-1. PWM Submodule Feature Support Submodule(s) SM0, SM1, SM2 SM3 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 190 Fractional Delay Input Capture Functions Yes No No Yes (FIFO depth is 1) Preliminary Freescale Semiconductor ...
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... CPU and peripheral clocks continue to run, but the CPU may stall for periods of time. PWM outputs Debug are driven or inactive as a function of CTRL2[DBGEN]. 7.1.3 Block Diagram The following figure is a block diagram of the PWM. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM) CAUTION Preliminary 191 ...
Page 192
... Introduction EXT_SYNC EXT_FORCE FAULT0-3 Fault Channel 0 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 192 Figure 7-1. PWM Block Diagram Preliminary PWMA0 PWMB0 Sub-Module 0 PWMX0 PWMA1 PWMB1 Sub-Module 1 PWMX1 PWMA2 PWMB2 Sub-Module 2 PWMX2 PWMA3 PWMB3 Sub-Module 3 PWMX3 Freescale Semiconductor ...
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... The PWM[n]_EXT_SYNC input signals are fed from the crossbar module. • The EXT_FORCE signal is fed from the crossbar module. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM) Mid-cycle reload 16 bit comparator ...
Page 194
... PWM can be synchronized to external circuitry. 7.2.6 EXT_FORCE - External Output Force Signal This input signal allows a source external to the PWM to force an update of the PWM outputs. In this manner, the PWM can be synchronized to external circuitry. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 194 Preliminary Freescale Semiconductor ...
Page 195
... PWM clocking. In this manner, the PWM can be synchronized to the on-chip source. This signal must be generated synchronously to the PWM's clock because it is not resynchronized in the PWM. MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM) Preliminary 195 ...
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... Address Register offset (hex) name PWM_SM0CNT PWM_SM0INIT W R PWM_ 2 SM0CTRL2 W R PWM_ 3 SM0CTRL Reserved W R PWM_ 5 SM0VAL0 W PWM_ R 6 SM0FRACVAL MC56F825x/4x Reference Manual, Rev. 2, 10/2010 196 CNT INIT INIT_SEL DT LDFQ Reserved VAL0 FRACVAL1 Preliminary FORCE_SEL CLK_SEL FORC PRSC Freescale Semiconductor 0 0 ...
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... PWM_ 10 SM0FRCTRL W R PWM_ 11 SM0OCTRL RUF 12 PWM_SM0STS PWM_ 13 SM0INTEN Reserved W R PWM_ 15 SM0TCTRL W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM VAL1 FRACVAL2 VAL2 FRACVAL3 VAL3 FRACVAL4 VAL4 FRACVAL5 VAL5 REF RF 0 RIE Reserved ...
Page 198
... PWM_ 3B SM1VAL3 W PWM_ R 3C SM1FRACVAL PWM_ 3D SM1VAL4 W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 198 DISX 0 0 Reserved CNT INIT INIT_SEL DT LDFQ VAL0 FRACVAL1 VAL1 FRACVAL2 VAL2 FRACVAL3 VAL3 FRACVAL4 VAL4 Preliminary DISB DISA DTCNT0 DTCNT1 0 FORCE_SEL CLK_SEL FORC PRSC Freescale Semiconductor 0 0 ...
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... W R PWM_ 47 SM1DTCNT0 W R PWM_ 48 SM1DTCNT1 PWM_SM2CNT PWM_SM2INIT W R PWM_ 62 SM2CTRL2 W R PWM_ 63 SM2CTRL W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 Freescale Semiconductor Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM FRACVAL5 VAL5 REF RF 0 RIE DISX 0 0 CNT INIT INIT_SEL DT LDFQ 14 13 ...
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... PWM_ 6F SM2VAL5 W R PWM_ 70 SM2FRCTRL W R PWM_ 71 SM2OCTRL RUF 72 PWM_SM2STS PWM_ 73 SM2INTEN W 15 MC56F825x/4x Reference Manual, Rev. 2, 10/2010 200 VAL0 FRACVAL1 VAL1 FRACVAL2 VAL2 FRACVAL3 VAL3 FRACVAL4 VAL4 FRACVAL5 VAL5 REF RF 0 RIE Preliminary PWMAFS PWMBFS PWMXFS 0 CMPF 0 CMPIE Freescale Semiconductor ...