MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 184
MC56F8245VLD
Manufacturer Part Number
MC56F8245VLD
Description
DSC 48K FLASH 60MHZ 44-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheets
1.TWR-56F8257.pdf
(88 pages)
2.MC56F8245VLD.pdf
(14 pages)
3.MC56F8245VLD.pdf
(2 pages)
4.MC56F8245VLD.pdf
(629 pages)
Specifications of MC56F8245VLD
Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
3K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
35
Data Ram Size
6 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 4 Channel
Package
44LQFP
Family Name
MC56F82xx
Maximum Speed
60 MHz
Data Bus Width
16 Bit
Interface Type
I2C/SCI/SPI
On-chip Dac
1-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC56F8245VLD
Manufacturer:
FREESCAL
Quantity:
269
Company:
Part Number:
MC56F8245VLD
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- TWR-56F8257 PDF datasheet
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- MC56F8245VLD PDF datasheet #3
- MC56F8245VLD PDF datasheet #4
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- Download datasheet (4Mb)
Resets
COMP2
COMP1
PWM Period
Figure 6-125. Variable PWM Waveform
Should we desire to update the duty cycle or period of the above waveform, we would
need to update the COMP1 and COMP2 values using the compare load feature.
>
6.6.2.17 Usage of the Capture Register
The capture register stores a copy of the counter's value when an input edge (positive,
negative, or both) is detected. After a capture event occurs, no further updating of the
capture register will occur until the SCTRL[IEF] (input edge flag) is cleared by writing a
zero to the SCTRL[IEF].
6.7
Resets
6.7.1 General
The TMR module can be reset only by the RST_B signal. This forces all registers to their
reset state and clears the OFLAG signal if it is asserted. The counter will be turned off
until the settings in the control register are changed.
Table 6-127. Reset Summary
Reset
Priority
Source
Characteristics
RST_B
n/a
Hardware Reset Full System Reset
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
184
Freescale Semiconductor
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