MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 72

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
72
PUDELAY
Reserved
PSTS0
Field
APD
PD1
9–4
10
3
2
1
to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the
current powered state of converter B.
0
1
ADC Converter A Power Status
This bit is asserted immediately following a write of "1" to PWR[PD0]. It is de-asserted PWR[PUDELAY]
ADC clock cycles after a write of "0" to PWR[PD0] if PWR[APD] is "0". This bit can be read as a status bit
to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the
current powered state of converter A.
0
1
Power Up Delay
This 6-bit field determines the number of ADC clocks provided to power up an ADC converter (after
setting PWR[PD0 or PD1] to 0) before allowing a scan to start. It also determines the number of ADC
clocks of delay provided in auto-powerdown (APD) and auto-standby (ASB) modes between when the
ADC goes from the idle to active state and when the scan is allowed to start. The default value is 13 ADC
clocks. Accuracy of the initial conversions in a scan will be degraded if PWR[PUDELAY] is set to too small
a value.
NOTE: PWR[PUDELAY] defaults to a value that is typically sufficient for any power mode. The latency of
Auto Powerdown
Auto-powerdown mode powers down converters when not in use for a scan. PWR[APD] takes
precedence over PWR[ASB]. When a scan is started in PWR[APD] mode, a delay of PWR[PUDELAY]
ADC clock cycles is imposed during which the needed converter(s), if idle, are powered up. The ADC will
then initiate a scan equivalent to that done when PWR[APD] is not active. When the scan is completed,
the converter(s) are powered down again.
NOTE: If PWR[ASB or APD] is asserted while a scan is in progress, that scan is unaffected and the ADC
0
1
This read-only bit is reserved and always has the value one.
Manual Power Down for Converter B
This bit forces ADC converter B to power down.
Asserting this bit powers down converter B immediately. The results of a scan using converter B will be
invalid while PWR[PD1] is asserted. When PWR[PD1] is cleared, converter B is either continuously
powered up (PWR[APD] = 0) or automatically powered up when needed (PWR[APD]=1).
ADC Converter B is currently powered up
ADC Converter B is currently powered down
ADC Converter A is currently powered up
ADC Converter A is currently powered down
Auto Powerdown Mode is not active
Auto Powerdown Mode is active
a scan can be reduced by reducing PWR[PUDELAY] to the lowest value for which accuracy is
not degraded. Refer to the data sheet for further details.
will wait to enter its low power state until after all conversions are complete and both ADC’s are
idle.
PWR[ASB and APD] are not useful in looping modes. The continuous nature of scanning means
that the low power state can never be entered.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
ADC_PWR field descriptions (continued)
Table continues on the next page...
Preliminary
Description
Freescale Semiconductor