MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 410

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
SPI operating in slave mode, the load of the shift register is controlled by the external
master, and back-to-back writes to the transmit data register are not possible. The SPTE
bit indicates when the next write can occur.
12.4.4 Error Conditions
The following flags signal SPI error conditions:
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12.4.4.1 Overflow Error
The overflow flag (OVRF) is set if the receive data register still has unread data from a
previous transaction when the capture strobe of bit 1 of the next transaction occurs. The
bit 1 capture strobe occurs in the middle of SCLK when the data length equals transaction
data length – 1. If an overflow occurs, all data received after the overflow and before the
OVRF bit is cleared does not transfer to the receive data register and does not set the SPI
receiver full bit (SPRF). The unread data that is transferred to the receive data register
before the overflow occurred can still be read. Therefore, an overflow error always
indicates the loss of data. Clear the overflow flag by reading the SPI status and control
register and then reading the SPI data register.
OVRF generates a receiver/error DSC interrupt request if the error interrupt enable bit
(ERRIE) is also set. It is not possible to enable MODF or OVRF individually to generate
a receiver/error DSC interrupt request. However, leaving MODFEN low prevents MODF
from being set.
If the DSC SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. The following figure shows how it is possible to miss an overflow.
The first part of the figure shows how it is possible to read the SCTRL register and the
DRCV register to clear the SPRF without problems. However, as illustrated by the
second transaction example, the OVRF bit can be set in between the time that the SCTRL
register and the DRCV register are read.
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• Overflow (OVRF) — Failing to read the DRCV register before the next data word
• Mode fault error (MODF) — The MODF bit indicates that the voltage on the slave
completes entering the shift register sets the OVRF bit. The new data word does not
transfer to the receive data register, and the unread data word can still be read. OVRF
is in the SPI status and control register.
select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status
and control register.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor