MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 341

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

messages ensures future expandability.with system management bus, a device can
provide manufacturer information, tell the system what its model/part number is, save its
state for a suspend event, report different types of errors, accept control parameters, and
return its status.
10.4.4.1 Timeouts
The T
is holding the clock low indefinitely or a master is intentionally trying to drive devices
off the bus. It is highly recommended that a slave device release the bus (stop driving the
bus and let SCL and SDA float high) when it detects any single clock held low longer
than T
communication and be able to receive a new START condition within the timeframe of
T
SMBus defines a clock low timeout, T
cumulative clock low extend time for a slave device, and specifies T
cumulative clock low extend time for a master device.
10.4.4.1.1 SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is
possible. Furthermore, the master cannot force the SCL line high to correct the error
condition. To solve this problem, the SMBus protocol specifies that devices participating
in a transfer must detect any clock cycle held low longer than a timeout value condition.
Devices that have detected the timeout condition must reset the communication. When
the I2C module is an active master, if it detects that SMBCLK low has exceeded the
value of T
byte in the transfer process. When the I2C module is a slave, if it detects the
T
START condition.
10.4.4.1.2 SCL High Timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T
occur in two ways:
Freescale Semiconductor
1. HIGH timeout detected after a STOP condition appears on the bus
2. HIGH timeout detected after a START condition, but before a STOP condition
TIMEOUT,MAX
TIMEOUT,MIN
appears on the bus
TIMEOUT,MIN
TIMEOUT,MIN
TIMEOUT,MIN
condition, it resets its communication and is then able to receive a new
.
. Devices that have detected this condition must reset their
parameter allows a master or slave to conclude that a defective device
, it must generate a stop condition within or after the current data
HIGH:MAX
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
, it assumes that the bus is idle. A HIGH timeout can
TIMEOUT
Preliminary
, of 35 ms, specifies T
Chapter 10 Inter-Integrated Circuit (I2C)
LOW:MEXT
LOW:SEXT
as the
as the
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