MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 34

DSC 48K FLASH 60MHZ 44-LQFP

MC56F8245VLD

Manufacturer Part Number
MC56F8245VLD
Description
DSC 48K FLASH 60MHZ 44-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8245VLD

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
3K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
35
Data Ram Size
6 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 4 Channel
Package
44LQFP
Family Name
MC56F82xx
Maximum Speed
60 MHz
Data Bus Width
16 Bit
Interface Type
I2C/SCI/SPI
On-chip Dac
1-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Core Block Diagram
1.3 Core Block Diagram
The DSC core is composed of several independent functional units. The program
controller, address generation unit (AGU) and data arithmetic logic unit (ALU) contain
their own register sets and control logic, allowing them to operate independently and in
parallel, increasing throughput. There is also an independent bit manipulation unit, which
provides for efficient bit-manipulation operations. Each functional unit interfaces with
the other units, memory, and the memory-mapped peripherals over the core's internal
address and data buses, and through the IP bus bridge (off core).
34
• Ability to generate interrupt with programmable rising or falling edge and
• Configurable drive strength: 4 mA/8 mA
software interrupt
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Freescale Semiconductor

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