MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 459

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.3.35 Transmit Buffer Time Stamp Register - Low Byte
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers
in the active transmit or receive buffer right after the EOF of a valid message on the CAN
bus. In case of a transmission, the CPU can only read the time stamp after the respective
transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN
bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set
to 0) during initialization mode. The CPU can only read the time stamp registers.
Read: Anytime when TXEx flag is set and the corresponding transmit buffer is selected
in CAN_TBSEL.
Write: Unimplemented
Address: CAN_TXFG_TSRL – F440h base + 3Fh offset = F47Fh
Freescale Semiconductor
Reset
Read
Write
TSR[15:8]
Bit
Reserved
Reserved
TSR[7:0]
15–8
15–8
Field
Field
7–0
7–0
15
0
(CAN_TXFG_TSRL)
14
0
This read-only bitfield is reserved and always has the value zero.
Time Stamp Register Bits 15-8
This read-only bitfield is reserved and always has the value zero.
Time Stamp Register Bits 7-0
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
CAN_TXFG_TSRH field descriptions
CAN_TXFG_TSRL field descriptions
11
0
10
0
Chapter 13 Freescale's Scalable Controller Area Network (MSCAN)
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
5
TSR[7:0]
0
4
0
3
0
2
0
1
0
0
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