MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 396

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map Registers
12.3.4 SPI Data Transmit Register (QSPI0_DXMIT)
The SPI data transmit register consists of a write-only data register. Writing data to this
register writes the data to the transmit data buffer. When the SPTE bit is set, new data
should be written to this register. If new data is not written while in master mode, a new
transaction will not begin until this register is written.
When selected in slave mode, the old data will be re-transmitted. When NOT selected
and in slave mode, transmit data will remain unchanged. All data should be written with
the LSB at bit 0. This register can only be written when the SPI is enabled, SPE = 1.
Address: QSPI0_DXMIT – F200h base + 3h offset = F203h
396
Reset
Read
Write
Bit
Field
Field
T15
T14
R6
R5
R4
R3
R2
R1
R0
15
14
6
5
4
3
2
1
0
T15
15
0
T14
14
0
Receive Data Bit 6
Receive Data Bit 5
Receive Data Bit 4
Receive Data Bit 3
Receive Data Bit 2
Receive Data Bit 1
Receive Data Bit 0
Transmit Data Bit 15
Transmit Data Bit 14
T13
13
0
T12
QSPI0_DRCV field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
T11
11
0
QSPI0_DXMIT field descriptions
Table continues on the next page...
T10
10
0
T9
0
9
Preliminary
T8
0
8
Description
Description
T7
0
7
T6
0
6
T5
0
5
T4
0
4
T3
0
3
Freescale Semiconductor
T2
0
2
T1
0
1
T0
0
0