MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 62

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
2.3.8 ADC Sample Disable Register (ADC_SDIS)
Address: ADC_SDIS – F080h base + 7h offset = F087h
2.3.9 ADC Status Register (ADC_STAT)
This register provides the current status of the ADC module. STAT[HLMTI and LLMTI]
bits are cleared by writing 1s to all asserted bits in the limit status register, LIMSTAT.
Likewise, the STAT[ZCI] bit, is cleared by writing 1s to all asserted bits in the zero
crossing status register, ZXSTAT. The STAT[EOSIx] bits are cleared by writing a one to
them.
Except for STAT[CIP0 and CIP1] this register's bits are sticky. Once set to a one state,
they require some specific action to clear them. They are not cleared automatically on the
next scan sequence.
Address: ADC_STAT – F080h base + 8h offset = F088h
62
Reset
Reset
Read
Read CIP0
Write
Write
Bit
Bit
15–0
CIP0
Field
Field
DS
15
15
15
1
0
CIP1
14
14
1
0
Disable Sample Bits
0
1
Conversion in Progress
Enable CLIST*[SAMPLEx].
Disable CLIST*[SAMPLEx] and all subsequent samples. Which samples are actually disabled will
depend on the conversion mode, sequential/parallel, and the value of CTRL2[SIMULT].
13
13
1
0
0
EOSI
12
12
1
1
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
EOSI
11
11
1
0
0
ADC_STAT field descriptions
ADC_SDIS field descriptions
Table continues on the next page...
ZCI
10
10
1
0
LLMT
1
0
9
9
I
Preliminary
HLMT
1
0
8
8
I
DS
Description
Description
0
0
7
7
0
0
6
6
0
0
5
5
UNDEFINED
0
0
4
4
0
0
3
3
Freescale Semiconductor
0
0
2
2
0
0
1
1
0
0
0
0