MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 14

DSC 48K FLASH 60MHZ 44-LQFP

MC56F8245VLD

Manufacturer Part Number
MC56F8245VLD
Description
DSC 48K FLASH 60MHZ 44-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr

Specifications of MC56F8245VLD

Core Processor
56800E
Core Size
16-Bit
Speed
60MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Ram Size
3K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
44-LQFP
Product
DSCs
Processor Series
56800E
Core
56800E
Device Million Instructions Per Second
60 MIPs
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
35
Data Ram Size
6 KB
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 4 Channel
Package
44LQFP
Family Name
MC56F82xx
Maximum Speed
60 MHz
Data Bus Width
16 Bit
Interface Type
I2C/SCI/SPI
On-chip Dac
1-chx12-bit
Number Of Timers
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Section Number
7.6
8.1
8.2
8.3
8.4
8.5
9.1
9.2
14
Interrupts.........................................................................................................................................................................293
Introduction.....................................................................................................................................................................295
8.1.1
8.1.2
8.1.3
Memory Map and Registers............................................................................................................................................296
8.2.1
Functional Description....................................................................................................................................................298
Clocks and Resets...........................................................................................................................................................300
Interrupts.........................................................................................................................................................................300
Overview.........................................................................................................................................................................301
9.1.1
9.1.2
Memory Map and Registers............................................................................................................................................302
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10
9.2.11
Overview..........................................................................................................................................................295
Features............................................................................................................................................................295
Block Diagram.................................................................................................................................................296
Crossbar Control Register n (XBXBCn).........................................................................................................298
Features............................................................................................................................................................301
Modes of Operation.........................................................................................................................................302
GPIO Pullup Enable Register (GPIOxA_PUR)...............................................................................................307
GPIO Data Register (GPIOxA_DR)................................................................................................................308
GPIO Data Direction Register (GPIOxA_DDR).............................................................................................308
GPIO Peripheral Enable Register (GPIOxA_PER).........................................................................................309
GPIO Interrupt Assert Register (GPIOxA_IAR).............................................................................................310
GPIO Interrupt Enable Register (GPIOxA_IENR)..........................................................................................311
GPIO Interrupt Polarity Register (GPIOxA_IPOLR)......................................................................................311
GPIO Interrupt Pending Register (GPIOxA_IPR)...........................................................................................312
GPIO Interrupt Edge Sensitive Register (GPIOxA_IESR)..............................................................................313
GPIO Push-Pull Mode Register (GPIOxA_PPMODE)...................................................................................313
GPIO Raw Data Register (GPIOxA_RAWDATA).........................................................................................314
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
General-Purpose Input/Output (GPIO)
Crossbar Switch (XBAR)
Chapter 8
Chapter 9
Preliminary
Title
Freescale Semiconductor
Page

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