MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 221

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.20 PWM SMx Output Trigger Control Register (PWM_SMnTCTRL)
Addresses: PWM_SM0TCTRL – F300h base + 15h offset = F315h
Freescale Semiconductor
Reset
Read
Write
OUT_TRIG_EN
Bit
Reserved
Reserved
Reserved
CMPIE
11–8
15–6
Field
Field
7–6
5–0
5–0
15
0
PWM_SM1TCTRL – F300h base + 45h offset = F345h
PWM_SM2TCTRL – F300h base + 75h offset = F375h
14
0
0
1
This read-only bitfield is reserved and always has the value zero.
This read-only bitfield is reserved and always has the value zero.
Compare Interrupt Enables
These bits enable the STS[CMPF] flags to cause a compare interrupt request to the CPU.
0
1
This read-only bitfield is reserved and always has the value zero.
Output Trigger Enables
These bits enable the generation of OUT_TRIG0 and OUT_TRIG1 outputs based on the counter value
matching the value in one or more of the VAL0-5 registers. VAL0, VAL2, and VAL4 are used to generate
OUT_TRIG0 and VAL1, VAL3, and VAL5 are used to generate OUT_TRIG1. The OUT_TRIGx signals are
only asserted as long as the counter value matches the VALx value, therefore up to six triggers can be
generated (three each on OUT_TRIG0 and OUT_TRIG1) per PWM cycle per submodule.
0
1
STS[RF] CPU interrupt requests disabled
STS[RF] CPU interrupt requests enabled
The corresponding STS[CMPF] bit will not cause an interrupt request.
The corresponding STS[CMPF] bit will cause an interrupt request.
OUT_TRIGx will not set when the counter value matches the VALx value.
OUT_TRIGx will set when the counter value matches the VALx value.
13
0
PWM_SMnINTEN field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SMnTCTRL field descriptions
11
0
0
10
0
0
9
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
Description
0
7
0
6
0
5
0
4
OUT_TRIG_EN
0
3
0
2
0
1
0
0
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