MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 574

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
17.3
17.3.1 Power Supervisor Control Register (PS_CTRL)
Address: PS_CTRL – F130h base + 0h offset = F130h
574
offset (hex)
Reset
Read
Write
Address
Bit
Reserved
HV27IE
HV21IE
0
1
15–4
Field
3
2
15
0
Memory Map and Registers
Register
PS_CTRL
PS_STS
name
14
0
This read-only bitfield is reserved and always has the value zero.
This bit allows the STS[LVI] bit to be set when the STS[LV27F] bit is clear. After a low voltage condition
occurs, set this bit and CTRL[HV21IE], clear CTRL[LV27IE and LV22IE], and an interrupt will be
generated once the voltage levels have returned to normal.
2.7 V High Voltage Interrupt Enable
0
1
This bit allows the STS[LVI] bit to be set when the STS[LV21F] bit is clear. After a low voltage condition
occurs, set this bit and CTRL[HV27IE], clear CTRL[LV27IE and LV21IE], and an interrupt will be
generated once the voltage levels have returned to normal.
2.1 V High Voltage Interrupt Enable
0
1
Disable setting the high voltage interrupt.
Enable setting the high voltage interrupt.
Disable setting the high voltage interrupt.
Enable setting the high voltage interrupt.
13
0
R
W
R
W
12
0
15
15
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
If both CTRL[HV27IE and HV21IE] are set, then both STS[LV27F and
LV21F] must be clear before STS[LVI] is set.
14
14
11
0
PS_CTRL field descriptions
13
13
Table continues on the next page...
10
0
12
12
0
0
9
Preliminary
11
11
0
8
10
10
0
0
Description
9
9
NOTE
0
7
8
8
0
6
7
7
0
5
6
6
0
4
5
5
LVI
4
4
0
3
Freescale Semiconductor
3
3
0
2
2
2
0
1
1
1
0
0
0
0