MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 219

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.18 PWM SMx Status Register (PWM_SMnSTS)
Addresses: PWM_SM0STS – F300h base + 12h offset = F312h
Freescale Semiconductor
Reset
Read
Write
Bit
PWMXFS
Reserved
Field
Field
RUF
REF
1–0
RF
15
14
13
12
15
0
0
PWM_SM1STS – F300h base + 42h offset = F342h
PWM_SM2STS – F300h base + 72h offset = F372h
RUF
14
0
PWMX Fault State
These bits determine the fault state for the PWMX output during fault conditions and STOP mode. It may
also define the output state during WAIT and DEBUG modes depending on the settings of
CTRL2[WAITEN] and CTRL2[DBGEN].
00
01
10
11
This read-only bit is reserved and always has the value zero.
Registers Updated Flag
This read only flag is set when one of the INIT, VALx, FRACVALx, or CTRL[PRSC] registers has been
written resulting in non-coherent data in the set of double buffered registers. Clear this bit by a proper
reload sequence consisting of a reload signal while MCTRL[LDOK] = 1. Reset clears this bit.
0
1
Reload Error Flag
This read/write flag is set when a reload cycle occurs while MCTRL[LDOK] is 0 and the double buffered
registers are in a non-coherent state (STS[RUF] = 1). Clear this bit by writing a logic one to this location.
Reset clears this bit.
0
1
Reload Flag
REF
No register update has occurred since last reload.
At least one of the double buffered registers has been updated since the last reload.
No reload error occurred.
Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
Output is forced to logic 0 state prior to consideration of output polarity control.
Output is forced to logic 1 state prior to consideration of output polarity control.
Output is tristated.
Output is tristated.
13
0
PWM_SMnOCTRL field descriptions (continued)
RF
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SMnSTS field descriptions
11
0
Table continues on the next page...
10
0
0
0
9
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
Description
0
7
0
0
6
0
5
0
4
0
3
CMPF
0
2
0
1
0
0
219