MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 212

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.10 PWM SMx Fractional Value Register 3 (PWM_SMnFRACVAL3)
Addresses: PWM_SM0FRACVAL3 – F300h base + Ah offset = F30Ah
212
Reset
Read
Write
FRACVAL3
Bit
Reserved
15–11
10–0
Field
Field
15
0
PWM_SM1FRACVAL3 – F300h base + 3Ah offset = F33Ah
PWM_SM2FRACVAL3 – F300h base + 6Ah offset = F36Ah
14
0
The 16-bit signed value in this buffered, read/write register defines the count value to set PWM23 high.
This register is not byte accessible.
NOTE: The VAL2 register is buffered. The value written does not take effect until MCTRL[LDOK] is set
Fractional Value 3 Register
These bits act as a fractional addition to the value in the VAL3 register which controls the PWMA turn off
timing. It is also used to control the fractional addition to the turn on delay of PWMB when
MCTRL[IPOLx]=0 in complementary mode, CTRL2[INDEP]=0.
NOTE: The FRACVAL3 register is buffered. The value written does not take effect until MCTRL[LDOK]
NOTE: FRCTRL[FRAC23_EN] should be set to 0 when the values of VAL2 and VAL3 cause the high or
This read-only bitfield is reserved and always has the value zero.
FRACVAL3
13
0
and the next PWM load cycle begins or CTRL[LDMOD] is set. VAL2 cannot be written when
MCTRL[LDOK] is set. Reading VAL2 reads the value in a buffer and not necessarily the value
the PWM generator is currently using.
is set and the next PWM load cycle begins or CTRL[LDMOD] is set. FRACVAL3 cannot be
written when MCTRL[LDOK] is set. Reading FRACVAL3 reads the value in a buffer and not
necessarily the value the PWM generator is currently using.
low time of the PWM output to be 3 cycles or less.
PWM_SMnVAL2 field descriptions (continued)
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SMnFRACVAL3 field descriptions
11
0
10
0
0
9
Preliminary
0
8
Description
Description
0
7
0
6
0
0
5
0
4
0
3
Freescale Semiconductor
0
2
0
1
0
0