MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 205

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.3 PWM SMx Control 2 Register (PWM_SMnCTRL2)
Addresses: PWM_SM0CTRL2 – F300h base + 2h offset = F302h
Freescale Semiconductor
Reset
Read
Write
PWM23_INIT
PWM45_INIT
Bit
WAITEN
DBGEN
INDEP
Field
15
14
13
12
11
15
0
PWM_SM1CTRL2 – F300h base + 32h offset = F332h
PWM_SM2CTRL2 – F300h base + 62h offset = F362h
14
0
Debug Enable
When set to one, the PWM will continue to run while the chip is in debug mode. If the device enters debug
mode and this bit is zero, then the PWM outputs will be disabled until debug mode is exited. At that point
the PWM pins will resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default state (in
which the PWM is disabled in debug mode). Failure to do so could result in damage to the motor or
inverter. For other types of motors (example: DC motors), this bit might safely be set to one, enabling the
PWM in debug mode. The key point is PWM parameter updates will not occur in debug mode. Any motors
requiring such updates should be disabled during debug mode. If in doubt, leave this bit set to zero.
WAIT Enable
When set to one, the PWM will continue to run while the chip is in WAIT mode. In this mode, the
peripheral clock continues to run but the CPU clock does not. If the device enters WAIT mode and this bit
is zero, then the PWM outputs will be disabled until WAIT mode is exited. At that point the PWM pins will
resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default state (in
which the PWM is disabled in WAIT mode). Failure to do so could result in damage to the motor or
inverter. For other types of motors (example: DC motors), this bit might safely be set to one, enabling the
PWM in WAIT mode. The key point is PWM parameter updates will not occur in this mode. Any motors
requiring such updates should be disabled during WAIT mode. If in doubt, leave this bit set to zero.
Independent or Complementary Pair Operation
This bit determines if the PWMA and PWMB channels will be independent PWMs or a complementary
PWM pair.
0
1
PWM23 Initial Value
This read/write bit determines the initial value for PWM23 and the value to which it is forced when
FORCE_INIT.
PWM45 Initial Value
PWMA and PWMB form a complementary PWM pair.
PWMA and PWMB outputs are independent PWMs.
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SMnCTRL2 field descriptions
11
0
Table continues on the next page...
10
0
INIT_SEL
0
9
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
0
8
Description
0
7
FORCE
0
0
6
0
5
FORCE_SEL
0
4
0
3
0
2
CLK_SEL
0
1
0
0
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