MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 344

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF
bit must be cleared by software by writing 1 to it in the interrupt routine. You can
determine the interrupt type by reading the Status Register.
10.4.6.1 Byte Transfer Interrupt
The transfer complete flag (TCF) bit is set at the falling edge of the ninth clock to
indicate the completion of a byte and acknowledgement transfer. When FACK is enabled,
TCF is then set at the falling edge of 8th clock to indicate the completion of byte.
10.4.6.2 Address Detect Interrupt
When the calling address matches the programmed slave address (I2C Address Register)
or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status
Register is set. The CPU is interrupted, provided the IICIE bit is set. The CPU must
check the SRW bit and set its Tx mode accordingly.
10.4.6.3 Exit from Low-Power/Stop Modes
The slave receive input detect circuit and address matching feature are still active on low
power modes (wait and stop). An asynchronous input matching slave address or general
call address brings the CPU out of low power/stop mode if the interrupt is not masked.
Therefore, TCF and IAAS both can trigger this interrupt.
344
SMBus SCL high SDA low timeout interrupt flag
SMBus SCL low timeout interrupt flag
Match of received calling address
Wakeup from stop interrupt
Complete 1-byte transfer
In master receive mode, the FACK bit must be set to zero
before the last byte transfer.
Interrupt Source
Arbitration lost
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Table 10-40. Interrupt Summary
Preliminary
NOTE
SHTF2
Status
ARBL
SLTF
IAAS
IAAS
TCF
IICIF
IICIF
IICIF
IICIF
IICIF
IICIF
Flag
Freescale Semiconductor
IICIE & SHTF2IE
IICIE & WUEN
Local Enable
IICIE
IICIE
IICIE
IICIE