MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 29

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Section Number
20.4 Resets..............................................................................................................................................................................619
20.5 Interrupts.........................................................................................................................................................................619
21.1 Introduction.....................................................................................................................................................................621
21.2 External Signal Description............................................................................................................................................622
21.3 Memory Map..................................................................................................................................................................623
21.4 Functional Description....................................................................................................................................................623
21.5 Clocks.............................................................................................................................................................................627
21.6 Interrupts.........................................................................................................................................................................628
Freescale Semiconductor
20.3.7
20.3.8
20.3.9
20.3.10 Flash Security Operation..................................................................................................................................617
20.5.1
20.5.2
21.1.1
21.1.2
21.4.1
21.4.2
Flash User Mode Illegal Operations................................................................................................................615
Calculate Data and IFR Block Signature Commands......................................................................................617
Effects of Wait and Stop Mode........................................................................................................................617
20.3.10.1 Set Flash Security...........................................................................................................................618
20.3.10.2 Back Door Access..........................................................................................................................618
20.3.10.3 JTAG Lockout Recovery...............................................................................................................619
General.............................................................................................................................................................619
Interrupt Operation...........................................................................................................................................619
Features............................................................................................................................................................621
Block Diagram.................................................................................................................................................621
JTAG Port Architecture...................................................................................................................................623
Master TAP Instructions..................................................................................................................................623
21.4.2.1
21.4.2.2
21.4.2.3
21.4.2.4
Bypass Instruction (BYPASS).......................................................................................................624
IDCODE.........................................................................................................................................624
TLM_SEL......................................................................................................................................624
TAP Controller...............................................................................................................................625
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Joint Test Action Group (JTAG) Port
Chapter 21
Preliminary
Title
Page
29