MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 20

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Section Number
13.1 Introduction.....................................................................................................................................................................417
13.2 External Signal Description............................................................................................................................................419
13.3 Memory Map and Register Definition............................................................................................................................420
20
13.1.1
13.1.2
13.1.3
13.2.1
13.2.2
13.2.3
13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.3.10 MSCAN Transmitter Message Abort Request Register (CANTARQ)...........................................................439
13.3.11 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)..................................................440
13.3.12 MSCAN Transmit Buffer Selection Register (CANTBSEL)..........................................................................441
13.3.13 MSCAN Identifier Acceptance Control Register (CANIDAC)......................................................................442
13.3.14 CANMISC.......................................................................................................................................................442
13.3.15 MSCAN Receive Error Counter Register (CANRXERR)..............................................................................443
13.3.16 MSCAN Transmit Error Counter Register (CANTXERR).............................................................................444
13.3.17 MSCAN Identifier Acceptance Registers (First Bank) (CANIDARn)............................................................445
13.3.18 MSCAN Identifier Mask Registers (First Bank) (CANIDMRn).....................................................................446
Block Diagram.................................................................................................................................................417
Features............................................................................................................................................................418
Modes of Operation.........................................................................................................................................419
RXCAN — CAN Receiver Input Pin..............................................................................................................419
TXCAN — CAN Transmitter Output Pin ......................................................................................................419
CAN System....................................................................................................................................................420
Programmer's Model of Message Storage.......................................................................................................420
MSCAN Control Register 0 (CANCTL0).......................................................................................................427
MSCAN Control Register 1 (CANCTL1).......................................................................................................430
MSCAN Bus Timing Register 0 (CANBTR0)................................................................................................432
MSCAN Bus Timing Register 1 (CANBTR1)................................................................................................433
MSCAN Receiver Flag Register (CANRFLG)...............................................................................................434
MSCAN Receiver Interrupt Enable Register (CANRIER)..............................................................................436
MSCAN Transmitter Flag Register (CANTFLG)...........................................................................................437
MSCAN Transmitter Interrupt Enable Register (CANTIER).........................................................................438
Freescale's Scalable Controller Area Network (MSCAN)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Chapter 13
Preliminary
Title
Freescale Semiconductor
Page