MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 101

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.4
3.4.1 External Pins
Each HSCMP has up to eight external analog input pins and one external output pin.
Each input pin can accept an input voltage that varies across the full operating voltage
range of the DSC.
Consult the data sheet to determine what functions are shared with analog inputs. As
shown in the block diagram, the Pn pins are connected to the comparator non-inverting
input. Mn pins are connected to the inverting input of the comparator.
Freescale Semiconductor
• The Window Control block is completely bypassed when WE = 0.
• If WE = 1, the comparator output is sampled on every peripheral clock when
• The Filter block is bypassed when not in use.
• The Filter block acts as a simple sampler if bypass_Filter_Block && FILTER_CNT
• The Filter block filters based on multiple samples when bypass_Filter_Block &&
• If enabled, the Filter block incurs up to 1 IP Bus additional latency penalty on COUT
• WE and SE are mutually exclusive.
WINDOW = 1 to generate COUTA. Sampling does not occur when WINDOW = 0.
= 0x1.
FILTER_CNT > 0x1:
because COUT (which is crossing clock domain boundaries) must be resynchronized
to the peripheral clock.
• If SE = 1, the external SAMPLE input is used as sampling clock.
• IF SE = 0, the divided peripheral clock is used as sampling clock.
Pin Descriptions
FILTER_CNT = 0X0
FILT_PER = 0X0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Figure 3-2. Filter Block Bypass Logic
SE
OR
Preliminary
AND
Chapter 3 High Speed Comparator (HSCMP)
bypass_Filter_Block
101