MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 235

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
CMPF
CFA1
CFA0
CFB1
CFB0
CFX1
CFX0
Field
REF
5–0
RF
13
12
11
10
9
8
7
6
This read only flag is set when one of the INIT, VALx, FRACVALx, or CTRL[PRSC] registers has been
written resulting in non-coherent data in the set of double buffered registers. Clear this bit by a proper
reload sequence consisting of a reload signal while MCTRL[LDOK] = 1. Reset clears this bit.
0
1
Reload Error Flag
This read/write flag is set when a reload cycle occurs while MCTRL[LDOK] is 0 and the double buffered
registers are in a non-coherent state (STS[RUF] = 1). Clear this bit by writing a logic one to this location.
Reset clears this bit.
0
1
Reload Flag
This read/write flag is set at the beginning of every reload cycle regardless of the state of MCTRL[LDOK].
Clear this bit by writing a logic one to this location. Reset clears this bit.
0
1
Capture Flag A1
This bit is set when a capture event occurs on the Capture A1 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Capture Flag A0
This bit is set when a capture event occurs on the Capture A0 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Capture Flag B1
This bit is set when a capture event occurs on the Capture B1 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Capture Flag B0
This bit is set when a capture event occurs on the Capture B0 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Capture Flag X1
This bit is set when a capture event occurs on the Capture X1 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Capture Flag X0
This bit is set when a capture event occurs on the Capture X0 circuit. This bit is cleared by writing a one
to this bit position. Reset clears this bit.
Compare Flags
These bits are set when the submodule counter value matches the value of one of the VALx registers.
Clear these bits by writing a 1 to a bit position.
0
1
No register update has occurred since last reload.
At least one of the double buffered registers has been updated since the last reload.
No reload error occurred.
Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
No new reload cycle since last STS[RF] clearing
New reload cycle since last STS[RF] clearing
No compare event has occurred for a particular VALx value.
A compare event has occurred for a particular VALx value.
PWM_SM3STS field descriptions (continued)
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Chapter 7 Enhanced Flex Pulse Width Modulator (eFlexPWM)
Description
235