MC56F8245VLD Freescale Semiconductor, MC56F8245VLD Datasheet - Page 367

• Manufacturer Part Number: MC56F8245VLD
• Description: DSC 48K FLASH 60MHZ 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8245VLD

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Ram Size: 3K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 44-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 6 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 44LQFP
• Family Name: MC56F82xx
• Maximum Speed: 60 MHz
• Data Bus Width: 16 Bit
• Interface Type: I2C/SCI/SPI
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Writing CTRL1[TE] bit from 0 to a 1 automatically loads the transmit shift register with
a preamble of 10 ones (if CTRL1[M] = 0) or 11 ones (if CTRL1[M] = 1). After the
preamble shifts out, control logic automatically transfers the data from the SCI data
register into the transmit shift register. A logic zero start bit automatically goes into the
least significant bit position of the transmit shift register. A logic one stop bit goes into
the most significant bit (MSB) position of the frame.
Hardware supports odd or even parity. When parity is enabled, the MSB of the data
character is replaced by the parity bit.
The transmit data register empty flag, STAT[TDRE], becomes set when the SCI data
register transfers a character to the transmit shift register. STAT[TDRE] indicates that the
SCI data register can accept new data from the internal data bus. If the transmitter empty
interrupt enable bit, CTRL1[TEIE], is also set, STAT[TDRE] generates a transmitter
interrupt request.
When the transmit shift register is not transmitting a frame and CTRL1[TE]=1, the TXD
pin goes to the idle condition, logic one. If at any time software clears CTRL1[TE], the
transmitter relinquishes control of the port I/O pin upon completion of the current
transmission, causing the TXD pin to go to a high z state.
If software clears CTRL1[TE] while a transmission is in progress (STAT[TIDLE] = 0),
the frame in the transmit shift register continues to shift out. Then transmission stops
even if there is data pending in the SCI data register. To avoid accidentally cutting off the
last frame in a message, always wait for STAT[TDRE] to go high after the last frame
before clearing CTRL1[TE].
To separate messages with preambles with minimum idle line time, use this sequence
between messages:
Freescale Semiconductor
2. Clear the transmit data register empty flag, STAT[TDRE], by first reading the SCI
3. Repeat step 2 for each subsequent transmission.
1. Write the last character of the first message to the DATA register.
2. Wait for STAT[TDRE] to go high while CTRL2[TFWM] = 00, indicating the
3. Queue a preamble by clearing and then setting CTRL1[TE].
4. Write the first character of the second message to the DATA register.
status register (STAT) and then writing to the SCI data register (DATA).
transfer of the last frame to the transmit shift register.
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Chapter 11 Queued Serial Communications Interface (QSCI)
367