ISL9305IRTWCLBZ-T Intersil, ISL9305IRTWCLBZ-T Datasheet - Page 8

• Manufacturer Part Number: ISL9305IRTWCLBZ-T
• Description: IC PMIC 800MA 3MHZ 16TQFN
• Manufacturer: Intersil

Specifications of ISL9305IRTWCLBZ-T

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 3: 0.9 V ~ 3.3 V, 350mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Soft-Start
The soft-start reduces the in-rush current during the start-up stage.
The soft-start block limits the current rising speed so that the
output voltage rises in a controlled fashion.
Overcurrent Protection
The overcurrent protection for DCD1 and DCD2 is provided on
ISL9305 for when an overload condition occurs. When the current at
P-Channel MOSFET is sensed to reach the current limit, the
internal protection circuit is triggered to turn off the P-Channel
MOSFET immediately.
DCD Short-Circuit Protection
The ISL9305 provides Short-Circuit Protection for both DCD1 and
DCD2. The feedback voltage is monitored for output short-circuit
protection. When the output voltage is sensed to be lower than a
certain threshold, the internal circuit will change the PWM
oscillator frequency to a lower frequencies in order to protect the
IC from damage. The P-Channel MOSFET peak current limit
remains active during this state.
Undervoltage Lock-out (UVLO)
An undervoltage lock-out (UVLO) circuit is provided on ISL9305.
The UVLO circuit block can prevent abnormal operation in the
event that the supply voltage is too low to guarantee proper
operation. The UVLO on VINDCD1 is set for a typical 2.2V with
100mV hysteresis. VINLDO1 and VINLDO2 are set for a typical
1.4V with 50mV hysteresis. When the input voltage is sensed to
be lower than the UVLO threshold, the related channel is
disabled.
DCDPG (DCD Power-Good)
ISL9305 offers an open-drain Power-Good signal with
programmable delay time for monitoring the converters DCD1
and DCD2 output voltages status.
When both DCD1 and DCD2 are enabled and their output
voltages are within the power-good window, an internal
power-good signal is issued to turn off the open-drain MOSFET so
the DCDPG pin voltage can be externally pulled high after a
programmed delay time. If either DCD1 or DCD2 output voltages
or both of them are not within the power-good window, the
DCDPG outputs an open-drain logic low signal after the
programmed delay time.
When there is only one DCD converter (either DCD1 or DCD2) is
enabled, then the DCDPG only indicates the status of this active
DCD converter. For example, if only DCD1 converter is enabled
and DCD2 converter is disabled, when DCD1 output is within the
power-good window, internal power-good signal will be issued to
turn off the open-drain MOSFET so the DCDPG pin voltage is
externally pulled high after the programmed delay time. If output
voltage of DCD1 is outside the power-good window, the DCDPG
outputs an open-drain logic low signal after the programmed
delay time. It is similar when only DCD2 is enabled and DCD1 is
disabled. When both converters are disabled, DCDPG always
outputs the open-drain logic low signal.
8
ISL9305
Low Dropout Operation
Both DCD1 and DCD2 converters feature the low dropout
operation to maximize the battery life. When the input voltage
drops to a level that the converter can no longer operate under
switching regulation to maintain the output voltage, the
P-Channel MOSFET is completely turned on (100% duty cycle).
The dropout voltage under such a condition is the product of the
load current and the ON-resistance of the P-Channel MOSFET.
Minimum required input voltage V
sum of output voltage plus the voltage drop across the inductor
and the P-Channel MOSFET switch.
Active Output Voltage Discharge For
DCD1/DCD2
The ISL9305 offers a feature to actively discharge the output
voltage of DCD1 and DCD2 via an internal bleeding resistor
(typical 115Ω) when the channel is disabled. This feature is
enabled by default, thus outputs can be disabled individually
through programming the control bit in DCD_PARAMETER
register.
Thermal Shutdown
The ISL9305 provides built-in thermal protection function with
thermal shutdown threshold temperature set at +155°C with
+25°C hysteresis (typical). When the die temperature is sensed
to reach +155°C, the regulator is completely shut down and as
the temperature is sensed to drop to +130°C (typical), the device
resumes normal operation starting from the soft-start.
Board Layout Recommendations
The ISL9305 is a high frequency switching charger and hence the
PCB layout is a very important design practice to ensure a
satisfactory performance.
The power loop is composed of the output inductor L, the output
capacitor C
make the power loop as small as possible and the connecting
traces among them should be direct, short and wide; the same
practice should be applied to the connection of the VIN pin, the
input capacitor C
The switching node of the converter, the SW pin, and the traces
connected to this node are very noisy, so keep the voltage
feedback trace and other noise sensitive traces away from these
noisy traces.
The input capacitor should be placed as close as possible to the
VIN pin. The ground of the input and output capacitors should be
connected as close as possible as well. In addition, a solid ground
plane is helpful for a good EMI performance.
The ISL9305 employs a thermal enhanced TQFN package with
an exposed pad. The exposed pad should be properly soldered on
thermal pad of the board in order to remove heat from the IC. The
thermal pad should be big enough for 9 vias as shown in
Figure 4.
OUT
, the SW pin and the PGND pin. It is important to
IN
and PGND.
IN
under such condition is the
November 8, 2010
FN7605.0