ISL9305IRTWCLBZ-T Intersil, ISL9305IRTWCLBZ-T Datasheet - Page 9

• Manufacturer Part Number: ISL9305IRTWCLBZ-T
• Description: IC PMIC 800MA 3MHZ 16TQFN
• Manufacturer: Intersil

Specifications of ISL9305IRTWCLBZ-T

• Topology: Step-Down (Buck) (2), Linear (LDO) (2)
• Function: Any Function
• Number Of Outputs: 4
• Frequency - Switching: 3MHz
• Voltage/current - Output 1: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 2: 0.8 V ~ 5.5 V, 800mA
• Voltage/current - Output 3: 0.9 V ~ 3.3 V, 350mA
• W/led Driver: No
• W/supervisor: No
• W/sequencer: No
• Voltage - Supply: 1.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
The ISL9305 offers an I
SCLK for the serial clock and SDAT for serial data respectively.
According to the I
for the clock and data signals to connect to a positive supply.
When the ISL9305 and the host use different supply voltages,
the pull-up resistors should be connected to the higher voltage
rail.
Signal timing specifications should satisfy the standard I
specification. The maximum bit rate is 400kb/s and more details
regarding the I
2
C Compatible Interface
S
S
SLAVE ADDRESS
DATA BYTE 1
SLAVE ADDRESS
2
FIGURE 4. EXPOSED THERMAL PAD
C specifications can be found from Philips.
2
DATA BYTE 2
C specifications, a pull-up resistor is needed
REGISTER ADDRESS
AUTO INCREMENT
2
C compatible interface, using two pins:
REGISTER ADDRESS
R/W
AUTO INCREMENT
0 A
9
R/W
A
0 A
REGISTER ADDRESS
A
OPTIONAL
DATA BYTE 2
REGISTER ADDRESS
FIGURE 7. I
REGISTER ADDRESS
AUTO INCREMENT
2
DATA BYTE N
C READ SPECIFYING REGISTER ADDRESS
2
FIGURE 6. I
C bus
OPTIONAL
ISL9305
A
A
REGISTER ADDRESS
AUTO INCREMENT
S
A
2
SLAVE ADDRESS
C WRITE
I
The ISL9305 serves as a slave device and the 7-bit default chip
address is 1101000, as shown in Figure 5 According to the I
specifications, here the value of Bit 0 determines the direction of
the message (“0” means “write” and “1” means “read”).
I
Figures 6, 7, and 8 show three typical I
protocols.
2
2
DATA BYTE 1
C Slave Address
C Protocol
A
BIT 7
DATA BYTE N
MSB
P
1
REGISTER ADDRESS
BIT 6
AUTO INCREMENT
1
REGISTER ADDRESS
AUTO INCREMENT
FIGURE 5. I
R/W
1
BIT 5
0
A
A
N
BIT 4
1
P
2
C SLAVE ADDRESS
BIT 3
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
0
SYSTEM HOST
ISL9305
2
C-bus transaction
A – ACKNOWLEDGE
N – NOT ACKNOWLEDGE
S – START
P – STOP
BIT 2
0
SYSTEM HOST
ISL9305
BIT 1
0
November 8, 2010
BIT 0
LSB
R/W
FN7605.0
2
C