ISL62882HRTZ Intersil, ISL62882HRTZ Datasheet - Page 13

• Manufacturer Part Number: ISL62882HRTZ
• Description: IC REG PWM 2PHASE BUCK 40TQFN
• Manufacturer: Intersil

Specifications of ISL62882HRTZ

• Applications: Controller, Intel IMVP-6.5™
• Voltage - Input: 5 V ~ 25 V
• Number Of Outputs: 1
• Voltage - Output: 0.0125 V ~ 1.5 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

V
and the current source discharges C
Since the ISL62882 works with V
amplitude and noise-free synthesized signals, the
ISL62882 achieves lower phase jitter than conventional
hysteretic mode and fixed PWM mode controllers. Unlike
conventional hysteretic mode converters, the ISL62882
has an error amplifier that allows the controller to
maintain a 0.5% output voltage accuracy.
Figure 7 shows the operation principles during load
insertion response. The COMP voltage rises during load
insertion, generating the master clock signal more
quickly, so the PWM pulses turn on earlier, increasing
the effective switching frequency, which allows for
higher control loop bandwidth than conventional fixed
frequency PWM controllers. The VW voltage rises as the
COMP voltage rises, making the PWM pulses wider.
During load release response, the COMP voltage falls. It
takes the master clock circuit longer to generate the
next master clock signal so the PWM pulse is held off
until needed. The VW voltage falls as the VW voltage
falls, reducing the current PWM pulse width. This kind of
behavior gives the ISL62882 excellent response speed.
The fact that both phases share the same VW window
voltage also ensures excellent dynamic current balance
between phases.
Diode Emulation and Period Stretching
ISL62882 can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side
MOSFET conducts when the current is flowing from
source to drain and does not allow reverse current,
emulating a diode. As Figure 8 shows, when LGATE is on,
the low-side MOSFET carries current, creating negative
voltage on the phase node due to the voltage drop across
the ON-resistance. The ISL62882 monitors the current
through monitoring the phase node voltage. It turns off
LGATE when the phase node voltage reaches zero to
prevent the inductor current from reversing the direction
and creating unnecessary power loss.
If the load current is light enough, as Figure 8 shows, the
inductor current will reach and stay at zero before the
next phase node pulse, and the regulator is in
discontinuous conduction mode (DCM). If the load
Crs
U G A T E
P H A S E
L G A T E
hits VW, the slave circuit turns off the PWM pulse,
IL
FIGURE 8. DIODE EMULATION
13
crs
, which are large
rs
.
ISL62882, ISL62882B
current is heavy enough, the inductor current will never
reach 0A, and the regulator is in CCM although the
controller is in DE mode.
Figure 9 shows the operation principle in diode
emulation mode at light load. The load gets
incrementally lighter in the three cases from top to
bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the inductor
current triangle the same in the three cases. The
ISL62882 clamps the ripple capacitor voltage V
mode to make it mimic the inductor current. It takes
the COMP voltage longer to hit V
the switching period. The inductor current triangles
move further apart from each other such that the
inductor current average value is equal to the load
current. The reduced switching frequency helps to
increase light load efficiency.
Start-up Timing
With the controller's V
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic high threshold. Figure 10 shows
the typical start-up timing when the ISL62882 is
configured for CPU VR application. The ISL62882 uses
digital soft-start to ramp-up DAC to the boot voltage of
1.1V at about 2.5mV/µs. Once the output voltage is
within 10% of the boot voltage for 13 PWM cycles
(43µs for frequency = 300kHz), CLK_EN# is pulled low
and DAC slews at 5mV/µs to the voltage set by the VID
pins. PGOOD is asserted high in approximately 7ms.
Similar results occur if VR_ON is tied to V
soft-start sequence starting 120µs after V
POR threshold.
Figure 11 shows the typical start-up timing when the
ISL62882 is configured for GPU VR application. The
ISL62882 uses digital soft start to ramp up DAC to the
Vcrs
Vcrs
Vcrs
iL
iL
iL
FIGURE 9. PERIOD STRETCHING
VW
VW
VW
CCM/DCM BOUNDARY
DD
LIGHT DCM
DEEP DCM
voltage above the POR
crs
, naturally stretching
DD
DD
, with the
crosses the
crs
FN6890.3
in DE