ISL6267HRZ Intersil, ISL6267HRZ Datasheet
ISL6267HRZ
Specifications of ISL6267HRZ
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ISL6267HRZ Summary of contents
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... CORE = 1.1V 0.96 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners 12V IN ...
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Simplified Application Circuit For High Power CPU Core VNB1 VNB2 VNB_SENSE µP VCORE_SENSE VO1 VO2 VO3 FIGURE 3. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 2 ISL6267 BOOT_NB UG1_NB ISEN1_NB PH1_NB ISEN2_NB LG1_NB ISUMN_NB ISUMP_NB VW_NB PWM2_NB COMP_NB NTC_NB FB_NB ...
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Simplified Application Circuit For AMD Torpedo Platform VNB1 VNB2 VNB_SENSE µP VCORE_SENSE VO1 VO2 FIGURE 4. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 3 ISL6267 NTC_NB ISEN1_NB BOOT_NB ISEN2_NB UG1_NB ISUMN_NB PH1_NB ISUMP_NB LG1_NB VW_NB COMP_NB PWM2_NB FB_NB FB2_NB VSEN_NB ...
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Simplified Application Circuit For Low Power CPU Core And NB +5V OPEN VNB1 optional VNB_SENSE µP OPEN +5V OPEN optional VCORE_SENSE VO1 FIGURE 5. TYPICAL APPLICATION CIRCUIT USING INDUCTOR DCR SENSING 4 ISL6267 ISEN2_NB ISEN1_NB BOOT_NB UG1_NB ISUMN_NB PH1_NB ISUMP_NB ...
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Simplified Application Circuit Showing Resistor Sensing +5V ISEN2_NB OPEN ISEN1_NB ISUMN_NB NB_N ISUMP_NB VW_NB optional COMP_NB FB_NB VSEN_NB VNB_SENSE RTN_NB PWROK µP SVD SVC OPEN ISEN1 +5V ISEN2 OPEN ISEN3 VW VW optional COMP COMP FB FB VSEN VSEN VCORE_SENSE ...
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Block Diagram SVD SERIAL SVC VID INTERFACE PWROK SLEEP D/A D/A MODE (PSI_L) VDD PROG1 OFFSET VOLTAGE PROG2 NTC_NB TEMP NTC MONITOR VR_HOT VW DAC1 + + RTN E COMP ...
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Pin Configuration COMP_NB PGOOD_NB Pin Descriptions PIN NUMBER SYMBOL 1 FB2_NB 2 FB_NB 3 COMP_NB 4 VW_NB 5 PGOOD_NB 6 SVD 7 PWROK 8 SVC 9 ENABLE 10 PGOOD 11 VR_HOT 12 NTC COMP ...
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Pin Descriptions (Continued) PIN NUMBER SYMBOL 16 ISEN3/FB2 17 ISEN2 18 ISEN1 19 VSEN 20 RTN 21 ISUMN 22 ISUMP 23 VDD 24 VIN 25 PROG1 26 BOOT1 27 UG1 28 PH1 29 LG1 30 PWM3 31 VCCP 32 LG2 ...
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... ISEN1_NB GND (Bottom Pad) Ordering Information PART NUMBER (Notes MARKING ISL6267HRZ ISL6267 HRZ ISL6267EVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...
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Table of Contents Core Performance On ISL6267EVAL1Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltage, V Battery Voltage, V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10° ...
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Electrical Specifications Operating Conditions: V Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) PARAMETER ISEN Imbalance Voltage Input Bias Current POWER-GOOD AND PROTECTION MONITORS PGOOD Low Voltage PGOOD Leakage Current PGOOD Delay GATE DRIVER UGATE Pull-Up ...
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Electrical Specifications Operating Conditions: V Boldface limits apply over the operating temperature range, -10°C to +100°C. (Continued) PARAMETER INPUTS ENABLE Leakage Current Slew Rate (for VID Change) Soft-Start Slew Rate SVI INTERFACE PWROK, SVC, SVD Input Logic High PWROK, SVC, ...
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... VDD and VDDNB, on one chip controlled by AMD’s™ SVI1™ protocol. VDD can be programmed for 1 3-phase operation. VDDNB can be configured for 1- or 2-phase operation. Both regulators use the Intersil patented R 3 Regulator) modulator. The R ™ modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings ...
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VW COMP V CRM MASTER CLOCK CLOCK1 PWM1 CLOCK2 PWM2 CLOCK3 PWM3 VW VCRS1 VCRS3 VCRS2 3 ™ FIGURE 9. R MODULATOR OPERATION PRINCIPLES IN LOAD INSERTION RESPONSE Diode Emulation and Period Stretching The ISL6267 can operate in diode emulation ...
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VDD SLEW RATE ENABLE 1.875mV/µs MetalVID 800µs DAC PGOOD PWROK VIN FIGURE 12. TYPICAL SOFT-START WAVEFORMS Power-On Reset Before the controller has sufficient bias to guarantee proper operation, the ISL6267 requires both a +5V input supply tied to V and ...
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TABLE 1. PRE-PWROK METAL VID CODES SVC SVD OUTPUT VOLTAGE ( The internal DAC circuitry begins to ramp Core and Northbridge VRs to the decoded pre-PWROK Metal VID output level. The digital ...
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SVID[6:0] VOLTAGE (V) SVID[6:0] 000_0000b 1.5500 010_0000b 000_0001b 1.5375 010_0001b 000_0010b 1.5250 010_0010b 000_0011b 1.5125 010_0011b 000_0100b 1.5000 010_0100b 000_0101b 1.4875 010_0101b 000_0110b 1.4750 010_0110b 000_0111b 1.4625 010_0111b 000_1000b 1.4500 010_1000b 000_1001b 1.4375 010_1001b 000_1010b 1.4250 010_1010b 000_1011b 1.4125 ...
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SVC SVD SLAVE ADDRESS PHASE SVI Bus Protocol The AMD processor bus protocol is compliant with SMBus send byte protocol for VID transactions (see Figure 14). During a send byte transaction, the processor sends the start sequence ...
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Rdroop + - Vdroop FB Idroop + E/A Σ COMP - DAC VDAC + + X 1 INTERNAL FIGURE 15. DIFFERENTIAL SENSING AND LOAD LINE IMPLEMENTATION As the load current increases from zero, the output voltage droops ...
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The ISL6267 will adjusts the phase pulse-width relative to the other phases to make ISEN1 ISEN2 when dcr1 dcr2 dcr3 ...
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REP RATE = 10kHz REP RATE = 25kHz REP RATE = 50kHz REP RATE = 100kHz REP RATE = 200kHz FIGURE 18. CURRENT BALANCING DURING DYNAMIC OPERATION. CH1 CH2 ISL6267 Modes of Operation ...
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Dynamic Operation Core VR and Northbridge VR behave the same during dynamic operation. The controller responds to VID-on-the-fly changes by slewing to the new voltage at the fixed 7.5mV/µs slew rate. During negative VID transitions, the output voltage decays to ...
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... A good NTC network can limit the output voltage drift to within 2mV recommended to follow the Intersil evaluation board layout and current sensing network parameters to minimize engineering time. V ...
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L C ----------------------------------------------------------- - = n R sum × R ------------- - ntcnet N × DCR ---------------------------------------- - R sum R + ------------- - ntcnet N For example, given 3.65kΩ, R sum R = 2.61kΩ, ...
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R and C form an R-C branch in parallel with lower impedance path than R at the beginning and C ...
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... VR VID FIGURE 27. VOLTAGE REGULATOR EQUIVALENT CIRCUIT Intersil provides a Microsoft Excel-based spreadsheet to help design the compensator and the current sensing network so that VR achieves constant output impedance as a stable system. Figure 29 shows a screenshot of the spreadsheet with active droop function is a dual-loop system consisting of a voltage loop and a droop loop, which is a current loop ...
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R isen that the ISEN voltages have minimal ripple and represent the DC current flowing through the inductors. Recommended values are R = 10kΩ and C = 0.22µ NTC Thermal Monitors and ...
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TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL 1 FB2_NB Place the compensator components (R25, R9, R24, C88, C51, C86, and C153) close to the controller. 2 FB_NB 3 COMP_NB 4 VW_NB Place the capacitor (C85) across VW, ...
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TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL 21 ISUMN Place the current sensing circuit in general proximity of the controller. Place capacitor Cn very close to the controller. 22 ISUMP Place the NTC thermistor next to VR1 ...
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TABLE 9. LAYOUT CONSIDERATIONS FOR THE ISL6267 CONTROLLER ISL6267 SYMBOL 45 RTN_NB Place the VSEN/RTN filter (C89, C90) in close proximity to the controller for good decoupling. 46 VSEN_NB 47 ISEN2_NB See ISEN1, ISEN2 and ISEN3 pins for layout guidelines ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing L48.6x6B 48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 9/09 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( 5. 75 TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 33 ISL6267 4X ...