LC4256V-75TN100C LATTICE SEMICONDUCTOR, LC4256V-75TN100C Datasheet - Page 5

• Manufacturer Part Number: LC4256V-75TN100C
• Description: MACH4000 ISP CPLD, 4256, TQFP100
• Manufacturer: LATTICE SEMICONDUCTOR
• Series: IspMACH 4000r

Specifications of LC4256V-75TN100C

• No. Of Macrocells: 256
• No. Of I/o's: 64
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.5ns
• Frequency: 322MHz
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: 0°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3. AND Array
Enhanced Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in product term clusters. Each product term
cluster is associated with a macrocell. The cluster size for the ispMACH 4000 family is 4+1 (total 5) product terms.
The software automatically considers the availability and distribution of product term clusters as it fits the functions
within a GLB. The logic allocator is designed to provide three speed paths: 5-PT fast bypass path, 20-PT Speed
Locking path and an up to 80-PT path. The availability of these three paths lets designers trade timing variability for
increased performance.
The enhanced Logic Allocator of the ispMACH 4000 family consists of the following blocks:
Figure 4 shows a macrocell slice of the Logic Allocator. There are 16 such slices in the GLB.
Figure 4. Macrocell Slice
• Product Term Allocator
• Cluster Allocator
• Wide Steering Logic
Individual Product
Term Allocator
Cluster
In[34]
In[35]
In[0]
n
Note:
Indicates programmable fuse.
n+1
to
n-1
to
n-2
to
Allocator
Cluster
5
5-PT
from
n+2
from
n-1
ispMACH 4000V/B/C/Z Family Data Sheet
from
from
n+1
n-4
PT0
PT1
PT2
PT3
PT4
PT75
PT76
PT77
PT78
PT79
From
n-4
PT80
PT81
PT82
Cluster 0
Cluster 15
Shared PT Clock
Shared PT Initialization
Shared PTOE
Steering Logic
SuperWIDE™
1-80
PTs
To n+4
To XOR (MC)
Fast 5-PT
Path