HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 237

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.10 Timer I/O Control Register (TIORA and TIORC)
The TIOR registers control the general registers (GR). Timer Z has four TIOR registers
(TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including
complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid.
TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORA
also selects the function of FTIOA or FTIOB pin.
Bit
7
6
5
4
3
Bit Name

IOB2
IOB1
IOB0

Initial
value
1
0
0
0
1
R/W

R/W
R/W
R/W

Description
Reserved
This bit is always read as 1.
I/O Control B2 to B0
GRB is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRB compare match
010: 1 output by GRB compare match
011: Toggle output by GRB compare match
GRB is an input capture register:
100: Input capture to GRB at the rising edge
101: Input capture to GRB at the falling edge
11X: Input capture to GRB at both rising and falling edges
Reserved
This bit is always read as 1.
Rev. 1.00 Sep. 16, 2005 Page 207 of 490
Section 13 Timer Z
REJ09B0216-0100