HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 372

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 17 I
(Master output)
17.4.4
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. For slave transmit mode operation timing,
refer to figures 17.9 and 17.10.
The transmission procedure and operations in slave transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0
2. When the slave address matches in the first frame following detection of the start condition,
3. If TDRE is set after writing last transmit data to ICDRT, wait until TEND in ICSR is set to 1,
4. Clear TRS for the end processing, and read ICDRR (dummy read). SCL is free.
5. Clear TDRE.
Rev. 1.00 Sep. 16, 2005 Page 342 of 490
REJ09B0216-0100
(Master output)
(Slave output)
processing
bits in ICCR1 to 1. (Initial setting) Set the MST and TRS bits in ICCR1 to select slave receive
mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At this time, if the 8th bit data (R/W) is 1, the TRS and ICSR bits in ICCR1 are
set to 1, and the mode changes to slave transmit mode automatically. The continuous
transmission is performed by writing transmit data to ICDRT every time TDRE is set.
with TDRE = 1. When TEND is set, clear TEND.
ICDRR
SCL
SDA
SDA
ICDRS
RDRF
RCVD
User
Slave Transmit Operation
2
Data n-1
C Bus Interface 2 (IIC2)
A
Figure 17.8 Master Receive Mode Operation Timing (2)
9
[5] Read ICDRR after setting RCVD
Data n-1
Bit 7
1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
[7] Read ICDRR,
6
and clear RCVD
Bit 1
7
Bit 0
Data n
8
A/A
9
Data n
[6] Issue stop
condition
[8] Set slave
receive mode