XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 334

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
MSCAN Controller
17.13.5 msCAN12 Bus Timing Register 1 (CBTR1).
Technical Data
334
CBTR1
$0103
RESET
R
W
SAMP
Bit 7
0
SAMP — Sampling
TSEG22 – TSEG10 — Time Segment
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in
1. In this case, PHASE_SEG1 must be at least two time quanta.
TSEG22
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point. (See
6
0
0 = One sample per bit.
1 = Three samples per bit.
TSEG21
Transmit point
Sample point
SYNC_SEG
5
0
MSCAN Controller
Table 17-7. Time segment syntax
TSEG20
4
0
A node in transmit mode will transfer a new
A node in receive mode will sample the bus
option is selected then this point marks the
System expects transitions to occur on the
at this point. If the three samples per bit
Table
value to the CAN bus at this point.
(1)
TSEG13
position of the third sample.
17-8.
bus during this period.
3
0
TSEG12
2
0
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
TSEG11
Figure
1
0
17-8)
TSEG10
Bit 0
0

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