PIC16F876A-E/SS Microchip Technology, PIC16F876A-E/SS Datasheet - Page 659

• Manufacturer Part Number: PIC16F876A-E/SS
• Description: 28 PIN, 14KB ENH FLASH, 368 RAM, 22 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F876A-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
Combined format:
S
(Code + A9:A8)
Slave Address
From slave to master
From master to slave
Slave Address R/W A Data A/A Sr
(write)
(read)
R/W A
data to this slave and reads data from this slave.
When a master does not wish to relinquish the bus (which occurs by generating a STOP condi-
tion), a repeated START condition (Sr) must be generated. This condition is identical to the start
condition (SDA goes high-to-low while SCL is high), but occurs after a data transfer acknowledge
pulse (not the bus-free state). This allows a master to send “commands” to the slave and then
receive the requested information or to address a different slave device. This sequence is shown
in
Figure A-8:
Figure
Slave Address
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(A7:A0)
A-8.
Sr = repeated
Start Condition
(n bytes + acknowledge)
(read or write)
Combined Format
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
Direction of transfer
may change at this point
Sr Slave Address
(Code + A9:A8)
P
(read)
Appendix A
R/W A Data A
DS31034A-page 34-7
Data
A P
34