USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 43

• Manufacturer Part Number: USBN9604-28MX
• Description: IC,Bus Controller,SOP,28PIN
• Manufacturer: National Semiconductor

Specifications of USBN9604-28MX

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

7.0 Register Set
7.2.13 Endpoint Control 0 Register (EPC0)
This register controls mandatory Endpoint Control 0.
EP
Endpoint. This field holds the 4-bit endpoint address. For Endpoint 0, these bits are hardwired to 0000
DEF
Default Address. When set, the device responds to the default address regardless of the contents of FAR6-0/EP03-0 fields.
When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared.
This bit aids in the transition from default address to assigned address. The transition from the default address
00000000000
sequence. This is necessary to complete the control sequence. However, the address must change immediately after this
sequence finishes in order to avoid errors when another control sequence immediately follows the SET_ADDRESS com-
mand.
On USB reset, the firmware has 10 mS for set-up, and should write 0x80 to the FAR register and 0x00 to the EPC0 register.
On receipt of a SET_ADDRESS command, the firmware must write 0x40 to the EPC0 register and 0x80
<assigned_function_address> to the FAR register. It must then queue a zero length IN packet to complete the status phase
of the SET_ADDRESS control sequence.
STALL
Setting this bit causes the chip to generate STALL handshakes under the following conditions:
1. The transmit FIFO is enabled and an IN token is received.
2. The receive FIFO is enabled and an OUT token is received.
Note: A SETUP token does not cause a STALL handshake to be generated when this bit is set.
Upon transmitting the STALL handshake, the RX_LAST and the TX_DONE bits in the respective Receive/Transmit Status
registers are set.
7.2.14 Transmit Status 0 Register (TXS0)
TCOUNT
Transmission Count. This bit Indicates the count of empty bytes available in the FIFO. This field is never larger than 8 for
Endpoint 0.
TX_DONE
Transmission Done. When set, this bit indicates that a packet has completed transmission. It is cleared when this register
is read.
ACK_STAT
Acknowledge Status. This bit indicates the status, as received from the host, of the ACK for the packet previously sent. This
bit is to be interpreted when TX_DONE is set to 1. It is set when an ACK is received; otherwise, it remains cleared. This bit
is also cleared when this register is read.
b
to an address assigned during bus enumeration may not occur in the middle of the SET_ADDRESS control
STALL
bit 7
Reserved
r/w
0
bit 7
-
-
(Continued)
bit 6
DEF
r/w
0
ACK_STAT
bit 6
CoR
0
bit 5
Reserved
-
-
TX_DONE
bit 4
CoR
bit 5
0
43
bit 3
0
bit 4
0
bit 3
r; hardwired to 0
bit 2
0
0
TCOUNT4-0
EP3-0
bit 2
0
r
bit 1
0
bit 1
0
bit 0
0
bit 0
b
.
0
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