USBN9604-28MX National Semiconductor, USBN9604-28MX Datasheet - Page 54

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USBN9604-28MX

Manufacturer Part Number
USBN9604-28MX
Description
IC,Bus Controller,SOP,28PIN
Manufacturer
National Semiconductor
Datasheets

Specifications of USBN9604-28MX

Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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8.0 Device Characteristics
Note: CKI in the following tables refers to the internal clock of the device and not to the signal frequency applied at XIN.
8.4 PARALLEL INTERFACE TIMING (MODE1-0 = 00
(3.0V< V
Symbol
1. Clock Internal: CKI = 48 MHz on this device
2. Memory Clock: MCLK = CKI/4 = 12 MHz
3. Time until next read or write occurs
t
t
t
Note: The setup time t
may switch at the same time.
t
t
t
t
RDH
t
t
t
RDV
WW
RW
WC
RC
DH
AS
AH
DS
CC
Address Setup Time
Address Hold Time
Read Pulse Width
Read Cycle Time
Data Output Valid after Read Low
Data Output Hold after Read High
Write Pulse Width
Write Cycle Time
Data Input Setup Time
Data Input Hold Time
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
D7-0 Output
AS
CS
A0
RD
Parameter
is defined relative to the first transition of either CS or RD. Both signals
2 3
2 3
1
1
Figure 25. Non-Multiplexed Mode Read Timing
(Continued)
t
AS
t
(Consecutive Read Cycles Shown)
RDV
t
RW
Valid
B
)
54
t
RDH
Conditions
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
t
RC
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
Valid
3/MCLK
3/MCLK
1/CKI
1/CKI
Min
25
0
0
2
8
Typ
20
Max
30
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS

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