QLX4600LIQSR Intersil, QLX4600LIQSR Datasheet - Page 14

• Manufacturer Part Number: QLX4600LIQSR
• Description: IC EQUALIZER REC 6.25GBPS 46QFN
• Manufacturer: Intersil

Specifications of QLX4600LIQSR

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The boost setting for equalizer channel k can be read as
a three digit ternary number across CP[k][A,B,C]. The
ternary value is established by the value of the resistor
between VDD and the CP[k][A,B,C] pin.
As a second option, the equalizer boost setting can be
taken from a set of registers programmed through a
serial bus interface (pins 16, 17, 45, and 46). Using this
interface, a set of registers is programmed to store the
boost level. A total of 21 registers are used. Registers 2
through 21 are parsed into four 5-bit words. Each 5-bit
word determines which of 32 boost levels to use for the
corresponding equalizer. Register 1 instructs the
QLx4600-SL30 to use registers 2 through 21 to set the
boost level rather than the control pins CP[k][A,B,C].
Both options have their relative advantages. The control
pin option minimizes the need for external controllers as
the boost level can be set in the board design resulting in
a compact layout. The register option is more flexible for
cases in which the optimum boost level will not be known
and can be changed by a host bus adapter with a small
number of pins. It is noted that the serial bus interface
can also be daisy-chained among multiple QLx4600-SL30
devices to afford a compact programmable solution even
when a large number of data lines need to be equalized.
Upon power-up, the default value of all the registers (and
register 1 in particular) is zero, and thus, the CP pins are
used to set the boost level. This permits an alternate
interpretation on setting the boost level. Specifically, the
CP3[A,B,C]
CP4[A,B,C]
CP2[C,B,A]
CP1[C,B,A]
PIN NAME
MODE
ENB
CLK
DO
DI
PIN NUMBER DESCRIPTION
18, 19, 20
21, 22, 23
39, 40, 41
42, 43, 44
TABLE 1. DESCRIPTIONS OF PINS USED TO SET EQUALIZATION BOOST LEVEL
16
17
24
45
46
14
Serial data input, CMOS logic. Input for serial data stream to program internal registers controlling
the boost for all four equalizers. Synchronized with clock (CLK) on pin 46. Overrides the boost
setting established on CP control pins. Internally pulled down.
Serial data output, CMOS logic. Output of the internal registers controlling the boost for all four
equalizers. Synchronized with clock on pin 46. Equivalent to serial data input on DI but delayed by
21 clock cycles.
Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Boost-level control mode input, CMOS logic. Allows serial programming of internal registers
through pins DI, ENB, and Clk when set HIGH. Resets all internal registers to zero and uses boost
levels set by CP pins when set LOW. If serial programming is not used, this pin should be grounded.
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the
boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ resistor.
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and CLK
pins only when the ENB pin is ‘LOW’. Internally pulled down.
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI is
latched on the rising clock edge. Clock speed is recommended to be between 10MHz and 20MHz.
Internally pulled down.
QLx4600-SL30
CP pins define the default boost level until the registers
are (if ever) programmed via the serial bus.
RESISTANCE BETWEEN CP PIN AND V
TABLE 2. MAPPING BETWEEN CP-SETTING RESISTOR
CP[A]
Open
Open
Open
Open
Open
Open
Open
Open
Open
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
AND PROGAMMED BOOST LEVELS
CP[B]
Open
Open
Open
25kΩ
25kΩ
25kΩ
Open
Open
Open
25kΩ
25kΩ
25kΩ
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
CP[C]
Open
25kΩ
Open
25kΩ
Open
25kΩ
Open
25kΩ
Open
25kΩ
Open
25kΩ
0Ω
0Ω
0Ω
0Ω
0Ω
0Ω
DD
November 19, 2009
BOOST LEVEL
SERIAL
10
12
14
15
16
17
19
21
23
24
26
28
31
0
2
4
6
8
FN6981.1