HS1-3282-8 Intersil, HS1-3282-8 Datasheet - Page 6

• Manufacturer Part Number: HS1-3282-8
• Description: IC,LINE TRANSCEIVER,CMOS,1 DRIVER,2 RCVR,DIP,40PIN,CERAMIC
• Manufacturer: Intersil

Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
If the receiver input data word string is broken before the
entire data word is received, the receiver will reset and
ignore the partially received data word.
If the transmitter is used to transmit consecutive data words,
each word will be separated by a four (4) bit “null” state (both
positive and negative outputs will maintain a zero (0) volt
level.)
Receiver Parity Status:
0 = Odd Parity
1 = Even Parity
No Source/Destination (S/D) in 25-Bit format.
Receiver Operation
Since the two receivers are functionally identical, only one
will be discussed in detail, and the block diagram will be
used for reference in this discussion. The receiver consists
of the following circuits:
BI-DIRECTIONAL
BI-DIRECTIONAL
BI-DIRECTIONAL
13 - 00
15 - 9
14 - 1
BlT#
BIT#
BIT#
7 - 0
ARINC BIT #
15
14
15
8
0
TABLE 3. ARINC 25-BIT DATA FORMAT
11 - 23
1 - 8
24
25
9
TABLE 2B. WORD 2 FORMAT
TABLE 4A. WORD 1 FORMAT
TABLE 4B. WORD 2 FORMAT
Parity Status
FUNCTION
FUNCTION
FUNCTION
Don’t Care
Label
MSB
Data
MSB
Data
Sign
LSB
Parity Status
FUNCTION
Label
MSB
Data
LSB
ARINC BIT#
ARINC BIT#
ARINC BlT#
27 - 14
23 -10
XXX
1 - 8
29
28
25
24
9
HS-3282
188
• The Line Receiver functions as a voltage level translator.
• The output of the Line Receiver is one of two inputs to the
• The incoming data, either Self-Test or ARlNC 429, is
• The derived data clock then shifts the data down a 32-Bit
• The Source/Destination (S/D) Decoder compares the user
• After the receiver data has been shifted down the shift
• The received data in the 32-bit holding register is placed
• The parity of the incoming word is checked and the status
• Assuming the user desires to access the data, he first sets
It transforms the 10 volt differential line voltage, ARINC
429 format, into 5 volt internal logic level.
Self-Test Data Selector (SEL). The other input to the
Data Selector is the Self-Test Signal from the Transmitter
section.
double sampled by the Word Gap Timer to generate a
Data Clock. The Receiver sample frequency (RCVCLK),
1MHz, or 125kHz, is generated by the Receiver/Transmit-
ter Timing Circuit. This sampling frequency is ten times the
Data Rate to ensure no data ambiguity.
long Data Shift Register (Data S/RI). The Data Word
Length is selectable for either 25 Bits or 32 Bits long by
the Control Signal (WLSEL). As soon as the data word is
completely received, an internal signal (WDCNT1) is gen-
erated by the Word Gap Timer Circuit.
set code (X and Y) with Bits 9 and 10 of the Data Word. If
the two codes are matched, a positive signal is generated
to enable the WDCNT1 signal to latch in the received
data. Otherwise, the data word is ignored and no latching
action takes place. The S/D Decoder can be Enabled and
Disabled by the control signal S/D ENB. If the data word is
latched, an indicator flag (D/R1) is set. This indicates a
valid data word is ready to be fetched by the user.
register, it is placed in a holding register. The device ready
flag will then be set indicating that data is ready to be
fetched. If the data is ignored and left in the holding regis-
ter, it will be written over when the next data word is
received.
on the bus in the form of two (2)16-bit words regardless of
whether the format is for 32 or 25-bit data words. Either
word can be accessed first or repeatedly until the next
received data word falls into the holding register.
(i.e., logic “0” for odd parity and logic “1” for even parity)
stored in the receiver latch and output on BD08 during the
Word No. 1.
the Data Select Line (SEL) to a Logic “0” level and pulses
the Enable (EN1) line. This action causes the Data
Selector (SELl) to select the first-data word, which con-
tains the label field and Enable it onto the Data Bus. To
obtain the second data word, the user sets the SEL line to
a Logic “1” level and pulse the Enable (EN1) line again.
The Enable pulse duration is matched to the user circuit
requirement needed to read the Data Word from the Data
Bus. The second Enable pulse is also used to reset the
Device Ready (D/R1) flip-flop. This completes a receiving
cycle.