HS1-82C55ARH-8 Intersil, HS1-82C55ARH-8 Datasheet

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HS1-82C55ARH-8

Manufacturer Part Number
HS1-82C55ARH-8
Description
Manufacturer
Intersil
Datasheet

Specifications of HS1-82C55ARH-8

Operating Temperature (max)
125C
Mounting
Through Hole
Lead Free Status / RoHS Status
Compliant
Radiation Hardened CMOS Programmable
Peripheral Interface
The Intersil HS-82C55ARH is a high performance, radiation
hardened CMOS version of the industry standard 8255A and
is manufactured using a hardened field, self-aligned silicon
gate CMOS process. It is a general purpose programmable
I/O device which may be used with many different
microprocessors. There are 24 I/O pins which are organized
into two 8-bit and two 4-bit ports. Each port may be
programmed to function as either an input or an output.
Additionally, one of the 8-bit ports may be programmed for
bidirectional operation, and the two 4-bit ports can be
programmed to provide handshaking capabilities. The high
performance, radiation hardness, and industry standard
configuration of the HS-82C55ARH make it compatible with
the HS-80C86RH radiation hardened microprocessor.
Static CMOS circuit design insures low operating power. Bus
hold circuitry eliminates the need for pull-up resistors. The
Intersil hardened field CMOS process results in performance
equal to or greater than existing radiation resistant products
at a fraction of the power.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95819. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
Ordering Information
5962R9581901QQC
5962R9581901VQC
ORDERING NUMBER
HS1-82C55ARH-8
HS1-82C55ARH-Q
MKT. NUMBER
TM
INTERNAL
1
1-888-INTERSIL or 321-724-7143
Data Sheet
TEMP. RANGE
-55 to 125
-55 to 125
(
o
C)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
|
Intersil and Design is a trademark of Intersil Corporation.
Features
• Electrically Screened to SMD # 5962-95819
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened
• Low Power Consumption
• Pin Compatible with NMOS 8255A and the Intersil 82C55A
• High Speed, No “Wait State” Operation with 5MHz
• 24 Programmable I/O Pins
• Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up
• Direct Bit Set/Reset Capability
• Enhanced Control Word Read Capability
• Hardened Field, Self-Aligned, Junction Isolated CMOS
• Single 5V Supply
• 2.0mA Drive Capability on All I/O Port Outputs
• Military Temperature Range . . . . . . . . . . . -55
Pinout
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . . . . <10
- Latch Up Free EPI-CMOS
- IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 A
HS-80C86RH
Resistors
Process
CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
August 2000
GND
PC7
PC6
PC5
PC4
PC0
PC1
PC2
PC3
PB0
PB1
PB2
PA3
PA2
PA1
PA0
RD
CS
A1
A0
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
MIL-STD-1835 CDIP2-T40
TOP VIEW
HS-82C55ARH
File Number
|
Copyright © Intersil Corporation 2000
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PA4
PA5
PA6
PA7
WR
RESET
D0
D1
D2
D3
D4
D5
D6
D7
VDD
PB7
PB6
PB5
PB4
PB3
o
C to 125
8
3191.2
rad(Si)/s
o
C

Related parts for HS1-82C55ARH-8

HS1-82C55ARH-8 Summary of contents

Page 1

... Detailed Electrical Specifications for these devices are contained in SMD 5962-95819. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Ordering Information INTERNAL ORDERING NUMBER MKT. NUMBER 5962R9581901QQC HS1-82C55ARH-8 5962R9581901VQC HS1-82C55ARH-Q 1 1-888-INTERSIL or 321-724-7143 August 2000 Features • Electrically Screened to SMD # 5962-95819 • QML Qualified per MIL-PRF-38535 Requirements • ...

Page 2

Pin Descriptions PIN SYMBOL NUMBERS TYPE PA0-7 1-4, 37-40 I/O PB0-7 18-25 I/O PC0-3 14-17 I/O PC4-7 10-13 I/O D0-7 27-34 I/O VDD 26 I GND and A1 ...

Page 3

Functional Diagram +5V POWER SUPPLIES GND BIDIRECTIONAL DATA BUS DATA BUS BUFFER RD WR READ/WRITE A1 CONTROL LOGIC A0 RESET CS AC Test Circuit V1 R1 FROM OUTPUT UNDER TEST R2 NOTE: Includes stray and jig capacitance. ...

Page 4

Waveforms TRLRH RD TPVRL INPUT TAVRL CS, A1 TRLDV FIGURE 1. MODE 0 (BASIC INPUT) TSLSH STB IBF TRLNL TSLIH INTR TSHNH RD INPUT FROM PERIPHERAL TPVSH FIGURE 3. MODE 1 (STROBED INPUT) DATA FROM CPU ...

Page 5

Burn-In Circuits PROGRAMMABLE PERIPHERAL INTERFACE STATIC CONFIGURATION NOTES: 1. VDD = 6.0V 0.5% 2. IDD <500 ...

Page 6

Irradiation Circuit CMOS PROGRAMMABLE PERIPHERAL INTERFACE +5. NOTE: 13. VDD = 5.5V Functional Description The HS-82C55ARH is a programmable peripheral ...

Page 7

Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and can be ...

Page 8

TABLE Data Bus - 3-State CONTROL WORD FIGURE 11. MODE SET CONTROL WORD FORMAT Mode Selection There are three basic modes ...

Page 9

Operating Modes Mode 0 (Basic Input/Output) This functional configuration provides simple input and output operations for each of the three ports. No handshaking it required, data is simply written to or read from a specific port. RD INPUT CS, A1, ...

Page 10

Mode 0 Port Definition ...

Page 11

Mode 0 Configurations (Continued) CONTROL WORD # CONTROL WORD # ...

Page 12

Mode 0 Configurations (Continued) CONTROL WORD # CONTROL WORD # ...

Page 13

TSLSH STB IBF TRLNL TSLIH INTR TSHNH RD INPUT FROM PERIPHERAL TPVSH FIGURE 16. MODE 1 (STROBED INPUT) Output Control Signal Definition OBF (Output Buffer Full F/F) The OBF output will go “low” to indicate that the CPU has written ...

Page 14

Operating Modes MODE 2 (Strobed Bidirectional Bus I/O) The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). “Handshaking” signals are provided ...

Page 15

MODE 0 IN PA0 In AP1 In PA2 In PA3 In PA4 In PA5 In PA6 In PA7 In PB0 In PB1 In PB2 In PB3 In PB4 In PB5 In PB6 In PB7 In PC0 In PC1 In PC2 ...

Page 16

Current Drive Capability Any output on Port can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C ...

Page 17

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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