ADCLK846BCPZ-REEL7 Analog Devices Inc, ADCLK846BCPZ-REEL7 Datasheet - Page 11

• Manufacturer Part Number: ADCLK846BCPZ-REEL7
• Description: 1.8V 6LVDS/12 CMOS Clock Fanout Buffer
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution)r

Specifications of ADCLK846BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HSTL, LVDS, LVPECL
• Output: CMOS, LVDS
• Frequency - Max: 1.2GHz
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
The ADCLK846 clock input is distributed to all output channels.
Each channel bank is pin programmable for either LVDS or
CMOS levels. This allows the selection of multiple logic
configurations ranging from 6 LVDS to 12 CMOS outputs,
along with other combinations using both types of logic.
CLOCK INPUTS
The differential inputs of the ADCLK846 are internally self-
biased. The clock inputs have a resistor divider, which sets the
common-mode level for the inputs. The complementary inputs
are biased about 30 mV lower than the true input to avoid
oscillations if the input signal ceases. See Figure 20 for
the equivalent input circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays
a guide for input logic compatibility. If a single-ended input is
desired, this can be accommodated by ac or dc coupling to one
side of the differential input. Bypass the other input to ground
by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 11. See Figure 28 through Figure 32 for
different termination schemes.
Table 8. Input Logic Compatibility
Supply (V)
3.3
2.5
1.8
3.3
2.5
1.8
1.5
3.3
2.5
1.8
Logic
CML
CML
CML
CMOS
CMOS
CMOS
HSTL
LVDS
LVPECL
LVPECL
LVPECL
Common Mode (V)
2.9
2.1
1.4
1.65
1.25
0.9
0.75
1.25
2.0
1.2
0.5
Rev. B | Page 11 of 16
Output Swing (V)
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
AC-COUPLED APPLICATIONS
When ac coupling is desired, the ADCLK846 offers two
options. The first option requires no external components
(excluding the dc blocking capacitor); it allows the user to
couple the reference signal onto the clock input pins (see
Figure 31).
The second option allows the use of the V
bias level for the ADCLK846. The V
to CLK and CLK through resistors. This method allows lower
impedance termination of signals at the ADCLK846 (see
Figure 32
The internal bias resistors are still in parallel with the external
biasing. However, the relatively high impedance of the internal
resistors allows the external termination to V
This is also useful if it is not desirable to offset the inputs slightly
as previously mentioned using only the internal biasing.
).
CLK
Figure 20. ADCLK846 Input Stage
9kΩ
9kΩ
AC-Coupled
Yes
Yes
Yes
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
Yes
REF
9.5kΩ
8.5kΩ
pin can be connected
V
CLK
GND
S
REF
Not allowed
Not allowed
Not allowed
pin to set the dc
DC-Coupled
Yes
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
REF
ADCLK846
to dominate.