ADCLK846BCPZ-REEL7 Analog Devices Inc, ADCLK846BCPZ-REEL7 Datasheet - Page 7

• Manufacturer Part Number: ADCLK846BCPZ-REEL7
• Description: 1.8V 6LVDS/12 CMOS Clock Fanout Buffer
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution)r

Specifications of ADCLK846BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HSTL, LVDS, LVPECL
• Output: CMOS, LVDS
• Frequency - Max: 1.2GHz
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4, 10, 13, 16, 19, 22
5
6
7
8
9
11
12
14
15
17
18
20
21
23
24
(25)
Mnemonic
V
CLK
CLK
V
CTRL_A
CTRL_B
SLEEP
OUT5 (OUT5B)
OUT5 (OUT5A)
OUT4 (OUT4B)
OUT4 (OUT4A)
OUT3 (OUT3B)
OUT3 (OUT3A)
OUT2 (OUT2B)
OUT2 (OUT2A)
OUT1 (OUT1B)
OUT1 (OUT1A)
OUT0 (OUT0B)
OUT0 (OUT0A)
EPAD
REF
S
Description
Reference Voltage.
Clock Input (Negative).
Clock Input (Positive).
Supply Voltage.
CMOS Input Control for Output 1 to Output 0. (0: LVDS, 1: CMOS.)
CMOS Input Control for Output 5 to Output 2. (0: LVDS, 1: CMOS.)
CMOS Input for Sleep Mode. (0: normal operation, 1: sleep.)
Complementary Side of Differential LVDS Output 5, or CMOS Output 5 on Channel B.
True Side of Differential LVDS Output 5, or CMOS Output 5 on Channel A.
Complementary Side of Differential LVDS Output 4, or CMOS Output 4 on Channel B.
True Side of Differential LVDS Output 4, or CMOS Output 4 on Channel A.
Complementary Side of Differential LVDS Output 3, or CMOS Output 3 on Channel B.
True Side of Differential LVDS Output 3, or CMOS Output 3 on Channel A.
Complementary Side of Differential LVDS Output 2, or CMOS Output 2 on Channel B.
True Side of Differential LVDS Output 2, or CMOS Output 2 on Channel A.
Complementary Side of Differential LVDS Output 1, or CMOS Output 1 on Channel B.
True Side of Differential LVDS Output 1, or CMOS Output 1 on Channel A.
Complementary Side of Differential LVDS Output 0, or CMOS Output 0 on Channel B.
True Side of Differential LVDS Output 0, or CMOS Output 0 on Channel A.
Exposed Paddle. The exposed paddle must be connected to ground.
NOTES:
1. EXPOSED PADDLE MUST BE CONNECTED TO GND.
CTRL_A
CTRL_B
V
CLK
CLK
REF
V
S
1
2
3
4
5
6
Figure 2. Pin Configuration
ADCLK846
(Not to Scale)
Rev. B | Page 7 of 16
TOP VIEW
PIN 1
INDICATOR
18 OUT2 (OUT2A)
17 OUT2 (OUT2B)
16 V
15 OUT3 (OUT3A)
14 OUT3 (OUT3B)
13 V
S
S
ADCLK846