ADCLK846BCPZ-REEL7 Analog Devices Inc, ADCLK846BCPZ-REEL7 Datasheet - Page 14

• Manufacturer Part Number: ADCLK846BCPZ-REEL7
• Description: 1.8V 6LVDS/12 CMOS Clock Fanout Buffer
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution)r

Specifications of ADCLK846BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HSTL, LVDS, LVPECL
• Output: CMOS, LVDS
• Frequency - Max: 1.2GHz
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCLK846
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the ADCLK846 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 27. Match the
far-end termination network to the PCB trace impedance and
provide the desired switching point. The reduced signal swing
may still meet receiver input requirements in some applications.
This can be useful when driving long trace lengths on less
critical nets.
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The ADCLK846 offers LVDS outputs
that are better suited for driving long traces where the inherent
noise immunity of differential signaling provides superior
performance for clocking converters.
INPUT TERMINATION OPTIONS
For single-ended operation, always bypass unused input to
GND as shown in Figure 31.
Figure 32 illustrates the use of the V
ance termination into V
to negate the 30 mV input offset with external resistor values.
For example, use 1.8 V CMOS with long traces to provide far-
end termination.
Figure 28. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations
Figure 27. CMOS Output with Far-End Termination
CMOS
CLK
CLK
10Ω
100Ω
S
/2. In addition, Figure 32 shows a way
(see Table 8)
50Ω
REF
V
S
100Ω
100Ω
to provide low imped-
CMOS
Rev. B | Page 14 of 16
Figure 32. Use of the V
Figure 30. Typical AC-Coupled or DC-Coupled LVPECL Configurations
Figure 31. Typical 1.8 V CMOS Configurations for Short Trace Lengths
CLK
CLK
Figure 29. Typical AC-Coupled or DC-Coupled CML Configurations
(see Table 8 for LVPECL DC Coupling Limitations)
(see Table 8 for CML Coupling Limitations)
CLK
CLK
(see Table 8 for CMOS compatibility)
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
REF
50Ω
50Ω
to Provide Low Impedance Termination into V
50Ω
50Ω
V
V
V
V
CC
CC
CC
CC
– 2V
– 2V
CLK
CLK
V
REF
S
/2