ADCLK846BCPZ-REEL7 Analog Devices Inc, ADCLK846BCPZ-REEL7 Datasheet - Page 4

• Manufacturer Part Number: ADCLK846BCPZ-REEL7
• Description: 1.8V 6LVDS/12 CMOS Clock Fanout Buffer
• Manufacturer: Analog Devices Inc
• Type: Fanout Buffer (Distribution)r

Specifications of ADCLK846BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121)
• Number Of Circuits: 1
• Ratio - Input:output: 1:6
• Differential - Input:output: Yes/Yes
• Input: CML, CMOS, HSTL, LVDS, LVPECL
• Output: CMOS, LVDS
• Frequency - Max: 1.2GHz
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 1.2GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADCLK846
TIMING CHARACTERISTICS
Table 2.
Parameter
LVDS OUTPUTS
CMOS OUTPUTS
LVDS-TO-CMOS OUTPUT SKEW
1
2
3
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Measured at rising edge of clock signal.
Calculated from SNR of ADC method.
Output Rise/Fall Time
Propagation Delay, CLK-to-LVDS Output
Output Skew
Additive Time Jitter
Output Rise/Fall Time
Propagation Delay, CLK-to-CMOS Output
Output Skew
Additive Time Jitter
LVDS Output(s) and CMOS Output(s)
Temperature Coefficient
All LVDS Outputs on the Same Part
All LVDS Outputs Across Multiple Parts
Integrated Random Jitter
Broadband Random Jitter
Crosstalk-Induced Jitter
Temperature Coefficient
All CMOS Outputs on the Same Part
All CMOS Outputs Across Multiple Parts
Integrated Random Jitter
Broadband Random Jitter
Crosstalk-Induced Jitter
on the Same Part
2
1
2
3
2
Symbol
t
t
t
t
R
PD
R
PD
, t
, t
F
F
Min
1.5
2.5
0.8
Rev. B | Page 4 of 16
Typ
2.0
260
3.2
2.2
260
135
2.0
54
74
86
150
525
56
100
Max
235
2.7
65
390
950
4.2
175
640
1.6
Unit
ps
ns
ps/°C
ps
ps
fs rms
fs rms
fs rms
fs rms
fs rms
ps
ns
ps/°C
ps
ps
fs rms
fs rms
fs rms
ns
Conditions
Termination = 100 Ω differential; 3.5 mA
20% to 80% measured differentially
V
BW = 12 kHz to 20 MHz, CLK = 1000 MHz
BW = 50 kHz to 80 MHz, CLK = 1000 MHz
BW = 10 Hz to 100 MHz, CLK = 1000 MHz
Input slew rate = 1 V/ns
Calculated from spur energy with an interferer
10 MHz offset from carrier
Termination = open
20% to 80%; CMOS load = 10 pF
10 pF load
BW = 12 kHz to 20 MHz, CLK = 200 MHz
Input slew = 2 V/ns; see Figure 11
Calculated from spur energy with an interferer
10 MHz offset from carrier
CMOS load = 10 pF and LVDS load = 100 Ω
ICM
= V
REF
, V
ID
= 0.5 V