CY8C3244LTI-123 Cypress Semiconductor Corp, CY8C3244LTI-123 Datasheet - Page 116

• Manufacturer Part Number: CY8C3244LTI-123
• Description: CY8C3244LTI-123
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3244LTI-123

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: QFN EP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 0.5KB
• Ram Memory Size: 2KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number: 001-56955 Rev. *J
Description Title: PSoC
Document Number: 001-56955
*C
2903576
04/01/10
®
3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC
MKEA
Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table.
Updated I
In page 1, updated internal oscillator range under Prescision programmable
clocking to start from 3 MHz.
Updated I
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section 12
Rem
oved some references to footnote [1].
Changed INC_Rn cycles from 3 to 2 (Table 4-1).
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout).
Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for V
and V
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level
Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.
Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64.
Updated V
Updated IDAC uncompensated gain error in Table 11-23.
Updated Delay from Interrupt signal input to ISR code execution from ISR code
in Table-71. Removed other line in table.
Added sentence to last paragraph of section 6.1.1.3.
Updated Tresp, high and low-power modes, in Table 11-22.
Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59.
Updated SNR condition in Table 11-18.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= V
Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3,
Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs
in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed
PPOR to PRES), Table 11-53 (changed title, values TBD), and Table 11-54
(changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1.
Changed I
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Changed sample rate row in Table 11-18.
Removed V
Changed Vioff values and changed CMRR value in Table 11-21.
Changed INL max value in Table 11-25.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-41.
Changed max response time value in Tables 11-54 and 11-56.
Change the Startup time in Table 11-64.
Added condition to intermediate frequency row in Table 11-70.
Added row to Table 11-54.
Added brown out note to Section 11.8.1.
DDD
CC
OUT
pins.
DD
REF
DDA
parameter in LCD Direct Drive DC Specs table.
values on page 1, page 5, and Table 11-2.
parameter in LCD Direct Drive DC Specs table.
specs in Table 11-19.
= 1.65 V rows and changed BWag value in Table 11-20.
DDD
< 3.3 V, SWD over USBIO pins value to Table 11-59.
PSoC
®
3: CY8C32 Family
®
)
Data Sheet
Page 116 of 119
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