CY8C3244LTI-123 Cypress Semiconductor Corp, CY8C3244LTI-123 Datasheet - Page 14

• Manufacturer Part Number: CY8C3244LTI-123
• Description: CY8C3244LTI-123
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3244LTI-123

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: QFN EP
• Screening Level: Industrial
• Pin Count: 48
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C32
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Operating Supply Voltage: 1.71 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 25
• Eeprom Memory Size: 0.5KB
• Ram Memory Size: 2KB
• Cpu Speed: 50MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
Table 4-3. Data Transfer Instructions
Document Number: 001-56955 Rev. *J
MOV A,Rn
MOV A,Direct
MOV A,@Ri
MOV A,#data
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC A, @A+DPTR
MOVC A, @A + PC
MOVX A,@Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
PUSH Direct
POP
XCH
XCH
XCH
XCHD A, @Ri
Rn,A
Rn,Direct
Rn, #data
Direct, A
Direct, Rn
Direct, Direct
Direct, @Ri
Direct, #data
@Ri, A
@Ri, Direct
@Ri, #data
DPTR, #data16
Mnemonic
Direct
A, Rn
A, Direct
A, @Ri
Move register to accumulator
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct byte
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move direct byte to indirect RAM
Move immediate data to indirect RAM
Load data pointer with 16-bit constant
Move code byte relative to DPTR to accumulator
Move code byte relative to PC to accumulator
Move external RAM (8-bit) to accumulator
Move external RAM (16-bit) to accumulator
Move accumulator to external RAM (8-bit)
Move accumulator to external RAM (16-bit)
Push direct byte onto stack
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with accumulator
Exchange low order indirect digit RAM with accumulator
Description
addressing mode.
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions.
page
15Table 4-4
lists the available Boolean instructions.
Table 4-3
PSoC
lists the various data transfer
®
3: CY8C32 Family
Bytes
1
2
1
2
1
2
2
2
2
3
2
3
1
2
2
3
1
1
1
1
1
1
2
2
1
2
1
1
Data Sheet
Page 14 of 119
Table 4-4
Cycles
1
2
2
2
1
3
2
2
2
3
3
3
2
3
2
3
5
4
4
3
5
4
3
2
2
3
3
3
on
[+] Feedback